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Very long instruction word
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1	Flexible Video Processing Platform for 8K UHD TV ELECTRONICS Sukjin Kim, Young-Hwan Park, Jaehyun Kim, Minsoo Kim, Wonchang Lee and Shihwa Lee Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:30 Parallel computing Computing Computer architecture Very long instruction word SIMD Instruction set
2	® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:26 Computing Parallel computing Computer architecture Manycore processors Digital signal processing Microprocessors Massively parallel processor array Multi-core processor Xeon Phi Massively parallel Digital signal processor Very long instruction word
3	Aging-Aware Compilation for GP-GPUs ATIEH LOTFI and ABBAS RAHIMI, University of California, San Diego LUCA BENINI, ETH Zurich and University of Bologna RAJESH K. GUPTA, University of California, San Diego General-purpos Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2015-07-13 19:18:56 Computing Computer architecture Parallel computing GPGPU Computer engineering OpenCL Graphics Core Next Compute kernel General-purpose computing on graphics processing units Very long instruction word Graphics processing unit Kernel
4	Microsoft Word - MEDEA2008-cfp_allineato.doc Add to Reading List Source URL: garga.iet.unipi.it Language: English - Date: 2008-07-22 08:11:16 Computing Concurrent computing Parallel computing Computer memory Computer architecture Microprocessors Electronic design automation Network on a chip Transactional memory Multi-core processor Very long instruction word Multiprocessing
5	Advanced Parallel Architecture Lesson 2 Annalisa Massini Introduction Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-03-03 11:01:50 Parallel computing Central processing unit Microprocessors Instruction set architectures Classes of computers Bit-level parallelism Reduced instruction set computing Instruction-level parallelism 64-bit computing Instruction set Very long instruction word Microarchitecture
6	1 Adaptive and Cooperative Execution Rodric M. Rabbah parts of this talk are based on an ASPLOS 04 paper with Add to Reading List Source URL: www.lcs.mit.edu Language: English - Date: 2004-11-20 00:25:45 Parallel computing Computing Computer architecture Computer engineering Thread Very long instruction word Hyper-threading Simultaneous multithreading
7	PDF Document Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2014-04-29 20:45:24 Computer architecture Computing Computer engineering Central processing unit Parallel computing Instruction set SIMD Processor register Microarchitecture Cell Very long instruction word
8	Automatically Generating Coarse Grained Software Pipelining from Declaratively Specified Communication Nilesh Mahajan* Sajith Sasidharan* Add to Reading List Source URL: www.hipc.org Language: English - Date: 2011-11-11 12:59:29 Parallel computing Compiler optimizations Actor model Software pipelining Futures and promises Very long instruction word Type system Central processing unit Programming language Computing Software engineering Programming language theory
9	Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers Stephen Hines, David Whalley, Gary Tyson Computer Science Department Florida State University Tallahassee, FL Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2006-08-24 08:01:51 Compiler optimizations Assembly languages Instruction scheduling Reduced instruction set computing Instruction set Branch predication Register renaming Very long instruction word Addressing mode Computer architecture Computing Computer engineering
10	Optimizing for Size: Exploring the Limits of Code Density Vincent M. Weaver ASPLOS XIV Poster Session, 8 MarchAbstract Add to Reading List Source URL: web.eece.maine.edu Language: English - Date: 2009-03-04 12:37:03 X86 Reduced instruction set computing Motorola 68000 family PA-RISC Instruction set Itanium ARM architecture Endianness DEC Alpha Computer architecture Instruction set architectures Very long instruction word