Massively parallel processor array

Results: 18



#Item
1® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO

® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO

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Source URL: www.hotchips.org

Language: English - Date: 2015-08-21 02:18:26
2Transactor-based debugging of massively parallel processor array architectures Markus Blocherer, Srinivas Boppu, Vahid Lari, Frank Hannig, Jürgen Teich Hardware/Software Co-Design University of Erlangen-Nuremberg

Transactor-based debugging of massively parallel processor array architectures Markus Blocherer, Srinivas Boppu, Vahid Lari, Frank Hannig, Jürgen Teich Hardware/Software Co-Design University of Erlangen-Nuremberg

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Source URL: www.mad-workshop.de

Language: English - Date: 2016-03-22 12:43:37
3GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator Jan Gray Gray Research LLC, Bellevue, WA, USA  Abstract— GRVI is an FPGA-efficient RISC-V RV32I soft

GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator Jan Gray Gray Research LLC, Bellevue, WA, USA Abstract— GRVI is an FPGA-efficient RISC-V RV32I soft

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Source URL: fpga.org

Language: English - Date: 2016-05-03 18:21:31
4Institut für Technische Informatik und Kommunikationsnetze Computer Engineering and Networks Laboratory  Prof. L. Thiele

Institut für Technische Informatik und Kommunikationsnetze Computer Engineering and Networks Laboratory Prof. L. Thiele

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Source URL: www.tik.ee.ethz.ch

Language: English - Date: 2016-02-29 10:12:36
5Institut für Technische Informatik und Kommunikationsnetze Computer Engineering and Networks Laboratory  Prof. L. Thiele

Institut für Technische Informatik und Kommunikationsnetze Computer Engineering and Networks Laboratory Prof. L. Thiele

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Source URL: www.tik.ee.ethz.ch

Language: English - Date: 2015-11-10 10:25:22
6Real-Time Systems manuscript No. (will be inserted by the editor) Mixed-Criticality Scheduling on Cluster-Based Manycores with Shared Communication and Storage Resources Georgia Giannopoulou · Nikolay Stoimenov ·

Real-Time Systems manuscript No. (will be inserted by the editor) Mixed-Criticality Scheduling on Cluster-Based Manycores with Shared Communication and Storage Resources Georgia Giannopoulou · Nikolay Stoimenov ·

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Source URL: www.tik.ethz.ch

Language: English - Date: 2015-07-22 10:25:28
7Kalray Accelerated Computing v2

Kalray Accelerated Computing v2

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Source URL: anciens-amis-cnrs.com

Language: English - Date: 2015-05-27 09:27:22
8Systems design 2012_Mise en page:48 Page216  Software engineering MANYCORELABS

Systems design 2012_Mise en page:48 Page216 Software engineering MANYCORELABS

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Source URL: www.teratec.fr

Language: English - Date: 2014-04-03 05:07:18
9Massively parallel processor array / Missoula /  Montana / Missoula / Hotel / Buffet / Hospitality industry / Tourism / Geography of the United States / Hilton Hotels Corporation / Hotel chains / Doubletree

2015 MPPA/MACOP Conference May 26 – 28, 2015 DoubleTree by Hilton Missoula, Montana

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Source URL: www.macop.com

Language: English - Date: 2015-02-26 15:13:05
10This is the author’s version of the work. The definitive work was published in Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009), 2009. FSM-Controlled Architectu

This is the author’s version of the work. The definitive work was published in Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009), 2009. FSM-Controlled Architectu

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Source URL: www12.informatik.uni-erlangen.de

Language: English - Date: 2009-10-28 16:18:44