Reduced instruction set computing

Results: 261



#Item
1Term-Level Verification of a Pipelined CISC Microprocessor Randal E. Bryant December, 2005 CMU-CS

Term-Level Verification of a Pipelined CISC Microprocessor Randal E. Bryant December, 2005 CMU-CS

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Source URL: www.cs.cmu.edu

Language: English - Date: 2006-01-09 17:18:43
2Ratio Games Raj Jain Washington University in Saint Louis Saint Louis, MOThese slides are available on-line at:

Ratio Games Raj Jain Washington University in Saint Louis Saint Louis, MOThese slides are available on-line at:

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Source URL: www.cs.wustl.edu

Language: English - Date: 2008-11-05 11:12:44
3eSi-1600 – 16-bit, low-cost & low-power CPU EnSilica’s eSi-1600 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. It offers similar performance t

eSi-1600 – 16-bit, low-cost & low-power CPU EnSilica’s eSi-1600 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. It offers similar performance t

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Source URL: www.avant-tek.com

Language: English - Date: 2014-10-14 01:56:25
4Efficient Cryptography on RISC-V Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria  Motivation

Efficient Cryptography on RISC-V Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation

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Source URL: www.iaik.tugraz.at

Language: English - Date: 2015-11-30 11:00:03
5RI5CY: User Manual May 2016 Revision 0.9 Andreas Traber () Michael Gautschi ()

RI5CY: User Manual May 2016 Revision 0.9 Andreas Traber () Michael Gautschi ()

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Source URL: www.pulp-platform.org

Language: English - Date: 2016-05-25 19:13:33
6ChapterIntroduction

ChapterIntroduction

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Source URL: www.warthman.com

Language: English - Date: 2003-03-07 17:54:29
7RISC-V Software Ecosystem Andrew Waterman UC Berkeley !  Tethered vs. Standalone Systems

RISC-V Software Ecosystem Andrew Waterman UC Berkeley ! Tethered vs. Standalone Systems

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Source URL: riscv.org

Language: English - Date: 2016-04-09 11:41:57
8MIPS Assembly Language Programmer’s Guide ASM-01-DOC  Your comments on our products and publications

MIPS Assembly Language Programmer’s Guide ASM-01-DOC Your comments on our products and publications

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Source URL: www.tik.ee.ethz.ch

Language: English - Date: 2009-09-02 12:08:50
9Secure AES Implementation on a 32-bit RISC-V Processor Advisor(s): Hannes Groß Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria

Secure AES Implementation on a 32-bit RISC-V Processor Advisor(s): Hannes Groß Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria

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Source URL: www.iaik.tugraz.at

Language: English - Date: 2016-02-24 05:00:01
10Advanced Parallel Architecture Lesson 2 Annalisa Massini Introduction

Advanced Parallel Architecture Lesson 2 Annalisa Massini Introduction

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Source URL: twiki.di.uniroma1.it

Language: English - Date: 2015-03-03 11:01:50