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Branch predication
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#	Item
1	Reducing the Cost of Conditional Transfers of Control by Using Comparison Specifications William Kreahling Western Carolina University Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2006-04-21 21:30:19 Branch predictor Branch misprediction Assembly languages Instruction set Branch predication Compiler optimization ARM architecture Processor register Classic RISC pipeline Computer architecture Central processing unit Instruction set architectures
2	Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers Stephen Hines, David Whalley, Gary Tyson Computer Science Department Florida State University Tallahassee, FL Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2006-08-24 08:01:51 Compiler optimizations Assembly languages Instruction scheduling Reduced instruction set computing Instruction set Branch predication Register renaming Very long instruction word Addressing mode Computer architecture Computing Computer engineering
3	Optimizing Software Data Prefetches with Rotating Registers Gautam Doshi Intel Corporation 2200, Mission College Blvd Santa Clara, CA 95052 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:06 Computer hardware Computer memory Software pipelining AMD 10h Loop unwinding CPU cache Branch predication Explicitly parallel instruction computing Compiler optimizations Computing Computer architecture
4	Parallel Architectures and Compilation Techniques PACT 2001 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2001-10-11 10:17:25 Central processing unit Parallel computing Branch predication Instruction set Branch misprediction Superscalar Computer architecture Computing Computer engineering
5	Microsoft Word - IHD_OS_Vol 4_Part 2_July_28_10.doc Add to Reading List Source URL: files.renderingpipeline.com Language: English - Date: 2013-09-24 10:33:32 Central processing unit Addressing mode Machine code Instruction set Branch predication Computer architecture Instruction set architectures Assembly languages
6	Optimizing and Reverse Engineering Itanium Binaries Noah Snavely EPIC (Explicitly Parallel Instruction Computing) architectures, such as the Intel IA-64 (Itanium), address common Add to Reading List Source URL: www.cs.arizona.edu Language: English - Date: 2010-09-27 23:22:30 Compiler optimizations Branch predication Itanium Explicitly parallel instruction computing Predicate Instruction scheduling Static single assignment form Instruction set Subroutine Computer architecture Computing Instruction set architectures
7	Countermeasures for the Simple Branch Prediction Analysis Giovanni Agosta and Gerardo Pelosi Dipartimento di Elettronica e Informazione Politecnico di Milano {agosta,pelosi}@elet.polimi.it Add to Reading List Source URL: eprint.iacr.org Language: English - Date: 2006-12-21 11:56:07 Compiler optimizations Compiler construction Branch predictor Branch predication Indirect branch Basic block ARM architecture Assembly language RSA Computer architecture Computing Software engineering
8	Predication Framework A Global Predication Compilation Framework David I. August Wen-mei W. Hwu IMPACT Compiler Group Add to Reading List Source URL: lslwww.epfl.ch Language: English - Date: 1999-02-19 04:45:45 Predicate Computing Instruction set Branch predication Control Conditional
9	SUN Microsystems Seminar December 18, 1998 EPIC Architectures and Compiler Technology Add to Reading List Source URL: lslwww.epfl.ch Language: English - Date: 1999-02-19 07:02:53 Central processing unit Compiler construction Explicitly parallel instruction computing Machine code Wen-mei Hwu Branch predication APT Compiler CPU cache Computer architecture Computing Computer hardware
10	Hot Chips 13 August 21, 2001 Itanium Performance Insights from the IMPACT Compiler Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:39:58 Central processing unit Parallel computing Itanium Compilers Compiler construction GNU Compiler Collection CPU cache Branch predication Symmetric multiprocessing Computing Computer architecture Software