Power-aware Computing: Measurement, Control, and Performance Analysis for Intel Xeon Phi Azzam Haidar∗ , Heike Jagode∗ , Asim YarKhan∗ , Phil Vaccaro∗ , Stanimire Tomov∗ , Jack Dongarra∗†‡ {haidar|jagode|

Source URL: icl.cs.utk.edu

AMBER: The How, What and Why on an Intel® Xeon Phi™ Perri Needham & Ross Walker (SDSC / UCSD)

Source URL: ambermd.org

High Order Seismic Simulations on the Intel Xeon Phi Processor (Knights Landing) Alexander Heinecke1 , Alexander Breuer2 , Michael Bader3 , and Pradeep Dubey1 1 2 3

Source URL: pcl.intel-research.net

Access We currently have a server with two Xeon Phi cards. The machine is called einstein.inf.ethz.ch. Get in contact with Timo Schneider if you want to have access to it. Usage To run a program on the MIC in native mode

Source URL: spcl.inf.ethz.ch

Available online at www.prace-ri.eu Partnership for Advanced Computing in Europe SHAPE Project Optimad Engineering srl.: RAPHI: Rarefied Flow Simulations on Xeon Phi Architecture

Source URL: www.prace-ri.eu

® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO

Source URL: www.hotchips.org

• Computing
• Parallel computing
• Computer architecture
• Manycore processors
• Digital signal processing
• Microprocessors
• Massively parallel processor array
• Multi-core processor
• Xeon Phi
• Massively parallel
• Digital signal processor
• Very long instruction word

DATE Venue Setting Capacity

Source URL: ieeecluster2016.org

• Concurrent computing
• Computing
• Parallel computing
• Computer architecture
• Xeon Phi
• Tutorial system
• Tutorial
• Xeon
• Slurm Workload Manager
• PGAS
• D
• Coffee

Op#mizing  and  Tuning  of  GPU  and  Xeon  Phi   Support  in  MVAPICH2   MVAPICH  User  Group  (MUG)  Mee#ng     by  

Source URL: mug.mvapich.cse.ohio-state.edu

• Computing
• Computer architecture
• Concurrent computing
• Parallel computing
• GPGPU
• Graphics hardware
• OpenCL compute devices
• Application programming interfaces
• MVAPICH
• OpenACC
• Graphics processing unit
• CUDA

High-Performance and Scalable Designs of Programming Models for Exascale Systems Talk at HPCAC-Switzerland (Marby Dhabaleswar K. (DK) Panda The Ohio State University

Source URL: www.hpcadvisorycouncil.com

• Computing
• Parallel computing
• Message Passing Interface
• Partitioned global address space
• Multi-core processor
• Xeon Phi
• K computer
• SHMEM
• Manycore processor

Lecture 2: Basic Performance Models For Extreme Scale Systems William Gropp www.cs.illinois.edu/~wgropp

Source URL: wgropp.cs.illinois.edu

• Computing
• Computer architecture
• Parallel computing
• Computer engineering
• Blue Gene
• Xeon Phi
• Xeon
• Intel Core