Flush+Flush: A Fast and Stealthy Cache Attack Daniel Gruss, Cl´ementine Maurice† , Klaus Wagner, and Stefan Mangard Graz University of Technology, Austria Abstract. Research on cache attacks has shown that CPU caches

Source URL: gruss.cc

Lecture 8: The Cache Oblivious Approach www.cs.illinois.edu/~wgropp Designing for Memory Hierarchy

Source URL: wgropp.cs.illinois.edu

• Cache
• Computer architecture
• Computing
• Analysis of algorithms
• Models of computation
• Computer science
• Computer engineering
• Cache-oblivious algorithm
• Computer memory
• Memory hierarchy
• Divide and conquer algorithms
• CPU cache

Efficient Cache Attacks on AES, and Countermeasures Eran Tromer1 2 , Dag Arne Osvik3 and Adi Shamir2 1 Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology,

Source URL: cs.tau.ac.il

• Cryptography
• Cache
• Computer memory
• Advanced Encryption Standard
• Side-channel attack
• Data Encryption Standard
• Cache memory
• Lookup table
• Cryptanalysis
• Tiny Encryption Algorithm
• Block cipher
• CPU cache

Scientific Computing Kernels on the Cell Processor Samuel Williams, John Shalf, Leonid Oliker Shoaib Kamil, Parry Husbands, Katherine Yelick Computational Research Division Lawrence Berkeley National Laboratory Berkeley,

Source URL: crd.lbl.gov

• Computing
• Computer memory
• Computer hardware
• Computer architecture
• Cell
• Direct memory access
• Emotion Engine
• Sparse matrix
• Scratchpad memory
• Loop nest optimization
• CPU cache
• SIMD

spcl.inf.ethz.ch @spcl_eth TIMO SCHNEIDER <> DPHPC Recitation Session 4

Source URL: spcl.inf.ethz.ch

• Computing
• Cache coherency
• Computer programming
• Parallel computing
• Computer memory
• Cache coherence
• Concurrent computing
• OpenMP
• False sharing
• Cache
• CPU cache

Design of Parallel and High Performance Computing HS 2014 Torsten Hoefler, Markus P¨ uschel Department of Computer Science ETH Zurich

Source URL: spcl.inf.ethz.ch

• Cache coherency
• Computing
• Computer hardware
• Computer architecture
• MESI protocol
• Cache
• Cache memory
• CPU cache

Auto-tuning the 27-point Stencil for Multicore Kaushik Datta2 , Samuel Williams1 , Vasily Volkov2 , Jonathan Carter1 , Leonid Oliker1 , John Shalf1 , and Katherine Yelick1 1 CRD/NERSC, Lawrence Berkeley National Laborat

Source URL: iwapt.org

• Compiler optimizations
• Computing
• Software engineering
• Software
• Loop nest optimization
• Stencil code
• Roofline model
• Stencil
• Program optimization
• Common subexpression elimination
• CPU cache
• Scalable locality

IEEE TRANSACTIONS ON COMPUTERS, VOL. ??, NO. ??, MONTHSoftware Support and Evaluation of Hardware Transaction Memory on Blue Gene/Q

Source URL: researcher.watson.ibm.com

• Computing
• Transaction processing
• Concurrency control
• Data management
• Computer memory
• Parallel computing
• Software transactional memory
• Transactional memory
• CPU cache
• Benchmark
• Blue Gene
• Linearizability

Cache-Timing Attack Against a Password-based Key Derivation Function Advisor(s): Raphael Spreitzer and Daniel Gruss Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Au

Source URL: www.iaik.tugraz.at

• Cryptography
• Computing
• Scrypt
• Key management
• PBKDF2
• Key derivation function
• CPU cache
• Password
• Cache
• Timing attack
• Lookup table

Seven at One Stroke: Results from a Cache-Oblivious ∗ Paradigm for Scalable Matrix Algorithms Michael D. Adams David S. Wise

Source URL: michaeldadams.org

• Computing
• Cache
• Computer hardware
• Computer memory
• Computer engineering
• Central processing unit
• Computer architecture
• Numerical software
• CPU cache
• Basic Linear Algebra Subprograms
• Cache-oblivious algorithm
• Page