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Parallelism
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571	INTRODUCING THE FR500 EMBEDDED MICROPROCESSOR DEVELOPED FOR DIGITAL CONSUMER PRODUCTS, THE FR500 MICROPROCESSOR ISSUES FOUR INSTRUCTIONS SIMULTANEOUSLY AND CAN BE Add to Reading List Source URL: www.ece.umd.edu Language: English - Date: 2002-05-07 12:21:33 Computer engineering Parallel computing Very long instruction word Instruction-level parallelism Branch predication Instruction set Processor register Computer architecture Central processing unit Computing
572	Fusion of Loops for Parallelism and Locality∗ Naraig Manjikian and Tarek S. Abdelrahman Department of Electrical and Computer Engineering Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 2001-12-23 06:53:26 Computer programming Loop optimization Automatic parallelization For loop Loop scheduling Parallel computing CPU cache Control flow Loop fusion Compiler optimizations Computing Software engineering
573	Trace Cache Leon Gu Dipti Motiani Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2003-10-13 07:06:40 Central processing unit CPU cache Cache Computer memory Parallel computing Microarchitecture Branch predictor Superscalar Instruction-level parallelism Computer architecture Computer hardware Computing
574	Exploiting Superword Level Parallelism with Multimedia Instruction Sets Samuel Larsen and Saman Amarasinghe Add to Reading List Source URL: groups.csail.mit.edu Language: English - Date: 2003-12-30 15:52:20 Compiler optimizations Software engineering Vectorization SIMD Stream processing Loop optimization Data parallelism Superword Level Parallelism Vector processor Computing Concurrent computing Parallel computing
575	Professor Shang-Hua Teng Department of Computer Science Boston University Add to Reading List Source URL: www.cs.bu.edu Language: English - Date: 2008-06-24 06:35:27 Mathematics ACM SIGACT Computational geometry Symposium on Parallelism in Algorithms and Architectures Daniel Spielman Symposium on Principles and Practice of Parallel Programming Year of birth missing David Eppstein Chandrajit Bajaj Computer science Theoretical computer science Applied mathematics
576	COM PUT ING PRACT ICES EPIC: Explicitly Parallel Add to Reading List Source URL: www.ece.iupui.edu Language: English - Date: 2006-02-14 18:13:49 Central processing unit Parallel computing Classes of computers Instruction set architectures Explicitly parallel instruction computing Instruction-level parallelism Very long instruction word Microarchitecture Superscalar Computer architecture Computing Computer hardware
577	Lecture 6: Vector Processing Professor David A. Patterson Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-02-11 20:19:26 Central processing unit Classes of computers Parallel computing Superscalar Vector processor Instruction set architectures Reduced instruction set computing Processor register Instruction-level parallelism Computer architecture Computing Computer hardware
578	Compiling for Parallelism & Locality Dependence Testing in General Add to Reading List Source URL: www.cs.colostate.edu Language: English - Date: 2007-08-14 13:37:07 Compiler optimizations Abstract algebra Linear algebra GCD test Loop optimization Banerjee test Dependence analysis Euclidean vector For loop Algebra Mathematics Compilers
579	Curriculum Vitae 1. Full Name: Add to Reading List Source URL: wwwmayr.in.tum.de Language: English - Date: 2011-01-31 03:06:26 Algorithm Computer science Symposium on Parallelism in Algorithms and Architectures Lecture Notes in Computer Science Science Computing Dagstuhl Leibniz-Gemeinschaft Theoretical computer science
580	An Empirical Study of Data Speculation Use on the Intel Itanium 2 Processor Markus Mock Add to Reading List Source URL: www.info.uni-karlsruhe.de Language: English - Date: 2005-07-01 08:51:12 Programming language implementation Advanced load address table Instruction set architectures Itanium Explicitly parallel instruction computing Speculative execution ALAT Instruction-level parallelism Processor register Computer architecture Computer hardware Central processing unit

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