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Explicitly parallel instruction computing
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1	Optimizing Software Data Prefetches with Rotating Registers Gautam Doshi Intel Corporation 2200, Mission College Blvd Santa Clara, CA 95052 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:06 Computer hardware Computer memory Software pipelining AMD 10h Loop unwinding CPU cache Branch predication Explicitly parallel instruction computing Compiler optimizations Computing Computer architecture
2	Code Reordering and Speculation Support for Dynamic Optimization Systems Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten, Wen-mei W. Hwu Center for Reliable and High-Performance Computing University of Illinois Urba Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:01 Out-of-order execution Electronics Very long instruction word Compiler optimization Instruction set Computer architecture Assembly languages Memory disambiguation Delay slot Computing Programming language implementation Explicitly parallel instruction computing
3	Optimizing and Reverse Engineering Itanium Binaries Noah Snavely EPIC (Explicitly Parallel Instruction Computing) architectures, such as the Intel IA-64 (Itanium), address common Add to Reading List Source URL: www.cs.arizona.edu Language: English - Date: 2010-09-27 23:22:30 Compiler optimizations Branch predication Itanium Explicitly parallel instruction computing Predicate Instruction scheduling Static single assignment form Instruction set Subroutine Computer architecture Computing Instruction set architectures
4	SUN Microsystems Seminar December 18, 1998 EPIC Architectures and Compiler Technology Add to Reading List Source URL: lslwww.epfl.ch Language: English - Date: 1999-02-19 07:02:53 Central processing unit Compiler construction Explicitly parallel instruction computing Machine code Wen-mei Hwu Branch predication APT Compiler CPU cache Computer architecture Computing Computer hardware
5	A Brief Analysis of the SPEC CPU2000 Benchmarks on the Intel® Itanium® 2 Processor James McCormick, HP Allan Knies, Intel All trademarks are the property of their respective owners Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:40:17 DEC Alpha Explicitly parallel instruction computing Computer architecture Instruction set architectures Itanium
6	HPL-PD Architecture Specification: Version 1.1 Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau Compiler and Architecture Research HPL[removed]R.1) February, 2000 (Revised) {kathail, schlansk, rau}@hpl.hp.com Add to Reading List Source URL: www.trimaran.org Language: English - Date: 2007-03-06 21:23:11 Central processing unit Parallel computing Classes of computers Explicitly parallel instruction computing Instruction-level parallelism Very long instruction word Instruction unit Superscalar Microarchitecture Computer architecture Computing Computer hardware
7	Trimaran ILP Reading List By Topical Category This is not intended to be a comprehensive and exhaustive bibliography of papers in the area of instruction-level parallel processing (ILP). Rather, this list concentrates on Add to Reading List Source URL: www.trimaran.org Language: English - Date: 2007-03-06 21:23:11 Multiflow Supercomputers Explicitly parallel instruction computing Programming Language Design and Implementation ALGOL 68 Very long instruction word Year of birth missing Computing Procedural programming languages Parallel computing
8	14 An Overview of the Trimaran Compiler Infrastructure Trimaran Tutorial Add to Reading List Source URL: www.trimaran.org Language: English - Date: 2007-03-06 21:23:11 Software Compiler Explicitly parallel instruction computing Instruction-level parallelism Instruction scheduling Program optimization Instruction set Inline expansion Register allocation Software engineering Compiler optimizations Computing
9	Documents Useful for Understanding Elcor Acyclic scheduling Inter-region scheduling [1]. Modulo scheduling Modulo scheduling of DO-loops [2]. Add to Reading List Source URL: www.trimaran.org Language: English - Date: 2007-03-06 21:23:11 Computer hardware Operations research Explicitly parallel instruction computing Hewlett-Packard Modulo Scheduling Planning Computing Technology
10	Machine-dependent ILP optimization capabilities 1. Framework The framework used for machine-dependent ILP optimizations in Trimaran provides advanced capabilities and support for experimenting with innovative, forward-lo Add to Reading List Source URL: www.trimaran.org Language: English - Date: 2007-03-06 21:23:11 Compiler construction Software Programming language implementation Planning Scheduling Branch predication Compiler Register allocation Explicitly parallel instruction computing Compiler optimizations Computing Software engineering