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#	Item
1	Gyrokinetic Particle-in-Cell Optimization on Emerging Multi- and Manycore Platforms Kamesh Madduria , Eun-Jin Imb , Khaled Z. Ibrahima , Samuel Williamsa , St´ephane Ethierc , Leonid Olikera a Computational Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-07-16 16:06:11 Computer architecture Computing Computer engineering Parallel computing Opteron Video cards Instruction set architectures Xeon Intel Core Cell Multi-core processor Fermi
2	Experiences with Sandia National Laboratories HPC applications and MPI performance Mahesh Rajan, Doug Doerfler, Richard Barrett, Joel Stevenson, Anthony Agelastos, Ryan Shaw and Hal Meyer MVAPICH User Group Meeting, Aug Add to Reading List Source URL: mug.mvapich.cse.ohio-state.edu Language: English - Date: 2015-11-20 13:17:46 Computer architecture Computing Computer engineering Appro Cray Sandy Bridge Opteron Xeon Piledriver Ivy Bridge Nehalem Intel Core
3	Optimization of a Lattice Boltzmann Computation on State-of-the-Art Multicore Platforms Samuel Williams∗,a,b , Jonathan Cartera , Leonid Olikera , John Shalfa , Katherine Yelicka,b a CRD/NERSC, b CS Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:48:36 Computer architecture Computing Computer hardware Computer memory Opteron Cell Multi-core processor Intel Core SPARC T5 Advanced Micro Devices Xeon CPU cache
4	hwloc: a Generic Framework for Managing Hardware Affinities in HPC Applications Fran¸cois Broquedis, J´erˆome Clet-Ortega, St´ephanie Moreaud, Nathalie Furmento, Brice Goglin, Guillaume Mercier, Samuel Thibault, Raym Add to Reading List Source URL: hal.inria.fr Language: English - Date: 2016-06-17 14:31:53 Computing Computer architecture Parallel computing Message Passing Interface Multi-core processor CPU cache Opteron Zen Thread Multiprocessing Multithreading Draft:Cache memory
5	Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms Samuel Williams∗†, Leonid Oliker∗, Richard Vuduc§, John Shalf∗, Katherine Yelick∗†, James Demmel† ∗ CRD/NERSC, Lawrenc Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-07 00:12:17 Computer memory Cache Computer architecture Compiler optimizations CPU cache Central processing unit Opteron Cell Sparse matrix-vector multiplication Loop nest optimization Multi-core processor Advanced Micro Devices
6	Cosmic Microwave Background Map-Making at the Petascale and Beyond Rajesh Sudarsan Julian Borrill Christopher Cantalupo Theodore Kisner Kamesh Madduri Leonid Oliker Horst Simon Yili Zheng Computational Research Division, Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-07-16 16:52:53 Parallel computing Supercomputers Multi-core processor Opteron CPU cache Cray Cosmic microwave background Pleiades Jaguar OpenMP Message Passing Interface
7	OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:58:43 Computer architecture Cache Central processing unit Microprocessors Computer memory CPU cache Stencil code Loop nest optimization Opteron POWER5 Cell Multi-core processor
8	Winner Best Paper, International Parallel & Distributed Processing Symposium (IPDPS), March 24-30, 2007, Long Beach, CA. Scientific Application Performance on Candidate PetaScale Platforms Leonid Oliker1 , Andrew Cannin Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-06-28 12:39:27 Parallel computing Supercomputers Concurrent computing Distributed computing architecture Cray X1 Supercomputer Cell Opteron Multi-core processor FLOPS Cray Jaguar
9	Microsoft Word - NakajimaK.doc Add to Reading List Source URL: iwapt.org Language: English - Date: 2009-08-18 06:49:13 Supercomputers Parallel computing Cray XT4 Cray Lis National Energy Research Scientific Computing Center Advanced Micro Devices Opteron Non-uniform memory access Multi-core processor Jaguar
10	Accurate emulation of CPU performance Tomasz Buchert1 , Lucas Nussbaum2 , and Jens Gustedt1 1 2 INRIA Nancy – Grand Est Add to Reading List Source URL: www.loria.fr Language: English Computer architecture Computing Computer engineering Clock signal Central processing unit CPU time Multi-core processor Load SpeedStep Clock rate Opteron Benchmark