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Stencil code
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#	Item
1	Report from Dagstuhl SeminarAdvanced Stencil-Code Engineering Edited by Christian Lengauer1 , Matthias Bolten2 , Robert D. Falgout3 , and Add to Reading List Source URL: www.infosun.fim.uni-passau.de - Date: 2015-09-22 06:12:25
2	Auto-tuning the 27-point Stencil for Multicore Kaushik Datta2 , Samuel Williams1 , Vasily Volkov2 , Jonathan Carter1 , Leonid Oliker1 , John Shalf1 , and Katherine Yelick1 1 CRD/NERSC, Lawrence Berkeley National Laborat Add to Reading List Source URL: iwapt.org Language: English - Date: 2009-08-03 20:59:23 Compiler optimizations Computing Software engineering Software Loop nest optimization Stencil code Roofline model Stencil Program optimization Common subexpression elimination CPU cache Scalable locality
3	High Performance Code Generation for Stencil Computation on Heterogeneous Multi-device Architectures Pei Li, Elisabeth Brunet, Raymond Namyst To cite this version: Add to Reading List Source URL: hal.inria.fr Language: English - Date: 2016-06-14 12:49:56 Computer architecture Computing Parallel computing GPGPU Software Graphics hardware Computational science OpenCL compute devices OpenCL General-purpose computing on graphics processing units Graphics processing unit Kernel
4	Optimizing Performance of Stencil Code with SPL Conqueror Alexander Grebhahn, Norbert Siegmund, Sven Apel University of Passau Passau, Germany Add to Reading List Source URL: www.infosun.fim.uni-passau.de Language: English - Date: 2014-01-23 03:14:20 Search algorithms Theoretical computer science Heuristic K-nearest neighbors algorithm Algorithm Configuration Mathematical optimization
5	OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:58:43 Computer architecture Cache Central processing unit Microprocessors Computer memory CPU cache Stencil code Loop nest optimization Opteron POWER5 Cell Multi-core processor
6	Auto-tuning the 27-point Stencil for Multicore Kaushik Datta2 , Samuel Williams1 , Vasily Volkov2 , Jonathan Carter1 , Leonid Oliker1 , John Shalf1 , and Katherine Yelick1 1 CRD/NERSC, Lawrence Berkeley National Laborat Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:44:43 Compiler optimizations Loop nest optimization Stencil code Roofline model Program optimization Stencil CPU cache Common subexpression elimination Scalable locality
7	MODESTO: Data-centric Analytic Optimization of Complex Stencil Programs on Heterogeneous Architectures Tobias Gysi Tobias Grosser Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-05-07 10:55:30 Visual arts Compiler optimizations Computational science Scientific modeling Simulation software Stencil code Stencil V. Tessellation Above Polytope model
8	MODESTO: Data-centric Analytic Optimization of Complex Stencil Programs on Heterogeneous Architectures Tobias Gysi Tobias Grosser Add to Reading List Source URL: htor.inf.ethz.ch Language: English - Date: 2015-05-20 10:03:50 Visual arts Compiler optimizations Computational science Scientific modeling Simulation software Stencil code Stencil V. Tessellation Above Polytope model
9	MODESTO: Data-centric Analytic Optimization of Complex Stencil Programs on Heterogeneous Architectures Tobias Gysi Tobias Grosser Add to Reading List Source URL: www.grosser.es Language: English - Date: 2015-08-09 08:54:49 Compiler optimizations Computational science Scientific modeling Simulation software Stencil code Stencil V. Tessellation Above Polytope model
10	A Framework for Enhancing Data Reuse via Associative Reordering Kevin Stock1 Louis-No¨el Pouchet3 1 Add to Reading List Source URL: www.grosser.es Language: English - Date: 2015-08-09 08:54:51 Software engineering Computer programming Compiler optimizations Computing Stencil code Loop optimization For loop Polytope model Optimizing compiler OpenMP Loop unrolling Foreach loop