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1	Privacy Notice. The Emergency Volunteer Corps of Nehalem Bay (EVCNB) is your local volunteer emergency preparedness organization. EVCNB asks for your name and contact information so that we have the ability to track y Add to Reading List Source URL: www.evcnb.org Language: English - Date: 2018-01-12 17:45:41
2	Experiences with Sandia National Laboratories HPC applications and MPI performance Mahesh Rajan, Doug Doerfler, Richard Barrett, Joel Stevenson, Anthony Agelastos, Ryan Shaw and Hal Meyer MVAPICH User Group Meeting, Aug Add to Reading List Source URL: mug.mvapich.cse.ohio-state.edu Language: English - Date: 2015-11-20 13:17:46 Computer architecture Computing Computer engineering Appro Cray Sandy Bridge Opteron Xeon Piledriver Ivy Bridge Nehalem Intel Core
3	Operational Intensity  Design of Parallel and High-Performance Computing Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-11-16 07:05:20 Sandy Bridge Intel Core Nehalem Cache Central processing unit Computer memory Sandy Bridge-E
4	Design of Parallel and High-Performance Computing Fall 2014 Lecture: Roofline Instructor: Torsten Hoefler & Markus Püschel Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-11-16 07:05:20 Sandy Bridge Intel Core Nehalem Cache Central processing unit Computer memory Sandy Bridge-E
5	Design of Parallel and High-Performance Computing Fall 2013 Lecture: Roofline Instructor: Torsten Hoefler & Markus Püschel Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2014-01-06 07:53:19 Sandy Bridge Intel Core Nehalem Cache Central processing unit Computer memory Sandy Bridge-E
6	H-Store: A Specialized Architecture for High-throughput OLTP Applications Evan Jones (MIT) Andrew Pavlo (Brown) 13th Intl. Workshop on High Performance Transaction Systems Add to Reading List Source URL: hpts.ws Language: English - Date: 2012-04-19 12:03:41 Data management Databases Online transaction processing Transaction processing Microprocessors Nehalem Xeon Multi-core processor
7	Operational Intensity  Design of Parallel and High-Performance Computing Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2014-11-23 12:29:14 Sandy Bridge Intel Core Nehalem Cache Central processing unit Computer memory Sandy Bridge-E
8	Government of India Directorate General of Supplies & Disposals Jeevan Tara Building, 5 Sansad Marg New DelhiTel Number Add to Reading List Source URL: www.aedindia.com Language: English - Date: 2015-03-26 09:40:30 Intel Core Intel Nehalem
9	Línea 6 - Nehalem Valley en Español Add to Reading List Source URL: www.columbiacountyrider.com Language: Spanish - Date: 2015-08-14 13:08:39
10	Opportunities for Parallelism in Matrix Multiplication FLAME Working Note #71 Tyler M. Smith∗ Robert A. van de Geijn∗ Add to Reading List Source URL: www.cs.utexas.edu Language: English - Date: 2014-01-10 19:11:37 Parallel computing Compiler optimizations Computer architecture CPU cache Central processing unit Computer memory Xeon Automatic parallelization Basic Linear Algebra Subprograms Nehalem Thread

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