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Computer architecture / Cache / Central processing unit / Microprocessors / Computer memory / CPU cache / Stencil code / Loop nest optimization / Opteron / POWER5 / Cell / Multi-core processor


OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St
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Document Date: 2012-09-06 23:58:43


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File Size: 2,78 MB

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