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#	Item
681	White Paper Using Digital Verification Techniques on Mixed-Signal SoCs with CustomSim and VCS March 2011 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:39:04 Electronic design Verilog-AMS Electronic test equipment SystemVerilog Signal generator Analog verification Verilog E System on a chip Electronic engineering Hardware description languages Hardware verification languages
682	White Paper Accelerating 20nm Double Patterning Verification with IC Validator Author Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:30:19 Design closure Signoff Multiple patterning Physical design Dermatopontin Standard cell DPT vaccine Validator Application-specific integrated circuit Electronic engineering Electronic design automation Design rule checking
683	Technical Backgrounder CustomExplorer Ultra Automated Regression for Mixed-Signal Verification April 2011 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:40:27 Logic design Hardware description languages SystemVerilog Verilog SPICE Netlist Logic simulation Simucad Electronic engineering Electronic design automation Digital electronics
684	White Paper De-risking Variation-Aware Custom IC Design with Solido Variation Designer and Synopsys HSPICE Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:28:58 Integrated circuits Solido Design Automation Process corners Waveform viewer Monte Carlo method Integrated circuit design SPICE Simulation Electrical network Electronic engineering Electronics Electromagnetism
685	White Paper MOS Device Aging Analysis with HSPICE and CustomSim August 2011 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:39:22 Semiconductors Hot carrier injection Semiconductor device fabrication MOSFET Reliability SPICE Electrical network Stress analysis Electronic engineering Electromagnetism Electronics
686	White Paper 新思科技Galaxy平台提供签核导向（SignoffDriven）的时序收敛工程变更指令（ECO）技术 March 2014 作者：新思科技技术营 Add to Reading List Source URL: www.synopsys.com Language: Chinese - Date: 2014-11-07 14:32:50
687	Success Story Synopsys and Ricoh Ricoh Delivers Software 5 Months in Advance for New Multi-Function Printer with Synopsys Virtualizer Add to Reading List Source URL: www.synopsys.com Language: English Synopsys Digital electronics Software development process High-level synthesis Logic synthesis Ricoh Electronic engineering Electronic design automation Hillsboro Oregon
688	White Paper 新思科技Galaxy平台提供簽核導向(SignoffDriven)之時序收斂工程變更指令(ECO)技術 March 2014 作者： Add to Reading List Source URL: www.synopsys.com Language: Korean - Date: 2014-11-07 14:32:50
689	Solution Overview Custom and Mixed-Signal Design Solution Unified Solution for Custom and Cell-Based Design and Verification January 2012 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:28:38 Signoff Synopsys Waveform viewer Standard cell Design rule checking Physical design Electronic circuit simulation Parasitic extraction SystemVerilog Electronic engineering Electronic design automation Digital electronics
690	White Paper PrimeTime® Mode Merging Reducing Analysis Cost for Multimode Designs August 2013 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:33:39 Static timing analysis Electronic design automation Signoff Timing closure

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