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Design rule checking
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1	Application Note: Design Rule Checking Written: Updated: March, 2002 Add to Reading List Source URL: judy.sourceforge.net Language: English - Date: 2004-09-10 16:20:39 C Struct Typedef Pointer Recursion XC CohenSutherland algorithm
2	Excellence. NO EXCUSES! Excerpt: DESIGN RULES! Tom Peters Add to Reading List Source URL: tompeters.com Language: English - Date: 2014-05-30 04:03:48 Richard Farson Virginia Postrel Rodney Fitch Design rule checking Food and drink Design Medicine Coffee in Seattle Pike Place Market Starbucks
3	ALINT™ Design Rule Checking Methodology Detects Design Flaws Early Aldec’s ALINT™ design analysis tool identifies critical design Add to Reading List Source URL: www.aldec.com Language: English - Date: 2014-09-11 15:01:15 Integrated circuits Aldec Electronic design VHDL Verilog Field-programmable gate array Application-specific integrated circuit Integrated circuit design Register-transfer level Electronic engineering Electronic design automation Hardware description languages
4	CCCG 2006, Kingston, Ontario, August 14–16, 2006 Range-Aggregate Proximity Detection for Design Rule Checking in VLSI Layouts R. Sharathkumar∗ Abstract Add to Reading List Source URL: cccg.ca Language: English - Date: 2008-10-27 22:59:14 Ordinary differential equations Group theory Spectral theory of ordinary differential equations Block design Mathematics Spectral theory Operator theory
5	Advanced Technology Option Micro-via Technology Within the powerful Pulsonix environment, advanced Micro-via technologies are easily created for everyday design engineers. Constraint Rules Driven Add to Reading List Source URL: www.pulsonix.com Language: English - Date: 2013-08-20 05:26:18 Electromagnetism Electronic design Via Printed circuit board PCB Surface-mount technology Design rule checking Three-dimensional integrated circuit Quad-flat no-leads package Electronic engineering Electronics manufacturing Electronics
6	Interactive High Speed Option Support for High Speed Designs Constraints Driven Design Rules Differential Pair Routing Add to Reading List Source URL: www.pulsonix.com Language: English - Date: 2013-08-20 05:26:24 Design rule checking Differential pair Electronic engineering Electronic design automation Routing
7	Datasheet IC Validator Overview IC Validator is a signoff DRC / LVS Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-04-22 17:53:38 Design Signoff Design rule checking Integrated circuit layout Physical design Design closure Tape-out Synopsys Physical verification Electronic engineering Electronic design automation Electronic design
8	Datasheet Galaxy Custom Designer LE Custom Layout Editing Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:29:15 Electronic design automation Design rule checking Process design kit Application-specific integrated circuit Integrated circuit design Signoff Electronic engineering Electronics Integrated circuits
9	White Paper Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform February 2014 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:38 Timing closure Physical design Design closure Integrated circuit design Static timing analysis ECO Synopsys Signal integrity Design rule checking Electronic engineering Electronic design automation Signoff
10	SUPPORTING GUIDE CASE STUDY High-speed Digital Board Design with Altium Designer Istvan Nagy, Electronics Design Engineer, Blue Chip Technology Add to Reading List Source URL: www.bluechiptechnology.co.uk Language: English - Date: 2011-05-06 07:47:36 Differential pair Routing PCB Signal integrity Altium Design rule checking Printed circuit board Cricket nets Electronic engineering Electronic design automation Altium Designer