Static timing analysis

Results: 58



#Item
1Proc. Asia South Pacific Design Automation Conf. (ASP-DAC), Shanghai, China, vol. 1, Jan. 2005, pp. I/2-I/7.  Opportunities and Challenges for Better Than Worst-Case Design Todd Austin, Valeria Bertacco, David Blaauw, an

Proc. Asia South Pacific Design Automation Conf. (ASP-DAC), Shanghai, China, vol. 1, Jan. 2005, pp. I/2-I/7. Opportunities and Challenges for Better Than Worst-Case Design Todd Austin, Valeria Bertacco, David Blaauw, an

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Source URL: web.eecs.umich.edu

Language: English - Date: 2016-04-03 10:58:13
2IEEE TRANSACTIONS ON COMPUTERS, VOL. 63, NO. XX, Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability

IEEE TRANSACTIONS ON COMPUTERS, VOL. 63, NO. XX, Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability

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Source URL: mesl.ucsd.edu

Language: English - Date: 2014-04-29 20:45:28
3ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling ∗ 2  Sibin Mohan1, Frank Mueller1 , William Hawkins2 , Michael Root3 , Christopher Healy3 and David Whalley4

ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling ∗ 2 Sibin Mohan1, Frank Mueller1 , William Hawkins2 , Michael Root3 , Christopher Healy3 and David Whalley4

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Source URL: www.cs.fsu.edu

Language: English - Date: 2005-09-23 10:35:49
4Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users FPGA 2 VIVA11000-ILT (v1.0)

Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users FPGA 2 VIVA11000-ILT (v1.0)

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Source URL: www.xilinx.com

Language: English - Date: 2014-06-17 12:40:57
5Vivado Design Suite Static Timing Analysis and Xilinx Design Constraints FPGA 3 FPGA-VSTAXDC-ILT (v1.0)

Vivado Design Suite Static Timing Analysis and Xilinx Design Constraints FPGA 3 FPGA-VSTAXDC-ILT (v1.0)

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Source URL: www.xilinx.com

- Date: 2015-05-22 13:56:45
    6Run-time Prediction of Execution Times of Stream-oriented Applications in Multiprocessors On-chip P. Poplavko, M. Pastrnak, T. Basten, J. van Meerbergen, M. Bekooij, P. de With

    Run-time Prediction of Execution Times of Stream-oriented Applications in Multiprocessors On-chip P. Poplavko, M. Pastrnak, T. Basten, J. van Meerbergen, M. Bekooij, P. de With

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    Source URL: www.es.ele.tue.nl

    Language: English - Date: 2005-07-08 02:46:37
    7WiST Group Lab Review Template

    WiST Group Lab Review Template

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    Source URL: www.symtavision.com

    Language: English - Date: 2012-10-31 05:31:39
    8Microsoft PowerPoint - Seshia-UsableVerif-Nov10

    Microsoft PowerPoint - Seshia-UsableVerif-Nov10

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    Source URL: fm.csl.sri.com

    Language: English - Date: 2010-11-15 20:44:04
    9A Compositional Framework for End-to-End Path Delay Calculation of Automotive Systems under Different Path Semantics Nico Feiertag and Kai Richter Symtavision GmbH, Braunschweig, Germany, {feiertag, richter}@symtavision.

    A Compositional Framework for End-to-End Path Delay Calculation of Automotive Systems under Different Path Semantics Nico Feiertag and Kai Richter Symtavision GmbH, Braunschweig, Germany, {feiertag, richter}@symtavision.

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    Source URL: www.symtavision.com

    Language: English - Date: 2012-10-31 05:01:40
    10

    PDF Document

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    Source URL: www.symtavision.com

    Language: English - Date: 2012-10-31 05:31:37