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Logic synthesis
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#	Item
1	Dissertation Reactive Synthesis: branching logic & parameteri zed systems Ayrat Khalimov Advisor: Roderick Bloem Add to Reading List Source URL: cgi.csc.liv.ac.uk Language: English - Date: 2018-05-18 11:56:24 Temporal logic Logic in computer science Model checkers Linear temporal logic Computation tree logic Model checking PAT Synthesis Mathematics
2	Synthesis of Logic Interpretations Jian Xiang, John Knight, Kevin Sullivan Department of Computer Science University of Virginia Charlottesville, VA USA {Jian,Knight,Sullivan}@cs.virginia.edu Add to Reading List Source URL: jianxiang.info Language: English - Date: 2017-09-23 07:40:56
3	Reactive Synthesis from Signal Temporal Logic Specifications Vasumathi Raman Alexandre Donzé Add to Reading List Source URL: dorsa.fyi Language: English - Date: 2018-08-10 01:41:28
4	Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks W. B. Toms, D. A. Edwards School of Computer Science, University of Manchester {tomsw,doug}@cs.man.ac.uk Add to Reading List Source URL: apt.cs.manchester.ac.uk Language: English - Date: 2014-05-13 09:16:47
5	Switching Logic Synthesis for Reachability∗ Ankur Taly Ashish Tiwari Computer Science Dept., Stanford University Add to Reading List Source URL: theory.stanford.edu - Date: 2011-03-08 18:45:54
6	Planning as Deductive Synthesis in Intuitionistic Linear Logic Lucas Dixon, Alan Smaill, and Alan Bundy {L.Dixon, A.Smaill, A.Bundy}@ed.ac.uk University of Edinburgh, Informatics, UK Add to Reading List Source URL: homepages.inf.ed.ac.uk - Date: 2006-10-18 10:00:12
7	2015 IEEE Symposium on Security and Privacy TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits Ebrahim M. Songhori∗ , Siam U. Hussain∗ , Ahmad-Reza Sadeghi† , Thomas Schneider† , Farinaz Kous Add to Reading List Source URL: www.ieee-security.org Language: English - Date: 2015-05-11 16:43:20 Electronic engineering Digital electronics Electronics Electronic design automation Electronic design Logic in computer science Cryptographic protocols Garbled circuit Boolean circuit Sequential logic Logic synthesis Standard cell
8	Datasheet Custom Compiler Visually-assisted Automation Introduction Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2016-08-09 19:15:50 Electronic design automation Electronic engineering Engineering Design Synopsys Signoff Logic synthesis Place and route Compiler EDA database Physical design
9	Advanced Logic Design Techniques in Asynchronous Sequential Circuit Synthesis Charles R. Bond http://www.crbond.com Add to Reading List Source URL: www.crbond.com Language: English - Date: 2013-07-09 13:31:54 Electronic engineering Digital electronics Electronics Electromagnetism Flip-flop Sequential logic Synchronous circuit Logic gate Counter Hazard Clock signal Logic synthesis