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Timing closure
Results: 48

#	Item
1	Datasheet SpyGlass DFT ADV RTL Testability Analysis and Improvement Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2016-07-28 07:15:29 Electronic engineering Electronic design automation Electronics Electronic design Integrated circuits Automatic test pattern generation Fault coverage SystemVerilog Timing closure Design for testing
2	Vivado Design Suite Tool Flow FPGA 1 FPGA-VDF-ILT (v1.0) Course Specification Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2015-05-21 13:22:32 Reconfigurable computing Hardware description languages Field-programmable gate array Xilinx Logic synthesis VHDL Application-specific integrated circuit Timing closure Electronic engineering Electronics Digital electronics
3	Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users FPGA 2 VIVA11000-ILT (v1.0) Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2014-06-17 12:40:57 Xilinx ISE Formal methods Field-programmable gate array Hardware description languages Xilinx Timing closure Static timing analysis Application-specific integrated circuit Design closure Electronic engineering Electronic design automation Electronics
4	Identifying and Predicting Timing-Critical Instructions to Boost Timing Speculation Jing Xin and Russ Joseph Department of EECS Northwestern University Add to Reading List Source URL: users.eecs.northwestern.edu Language: English - Date: 2011-12-14 11:29:00 Computer memory Central processing unit Branch predictor Hazard CPU cache Dynamic random-access memory Dynamic voltage scaling Microarchitecture Design closure Computer hardware Electronic engineering Computer architecture
5	Datasheet PrimeTime Golden Timing Signoff Solution and Environment Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 15:15:31 Signal integrity Design closure Static timing analysis Timing closure Delay calculation Application-specific integrated circuit Design flow Clock distribution network Parasitic extraction Electronic engineering Electronic design automation Signoff
6	Datasheet Verdi3 Automated Debug System Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-04-29 10:15:28 Hardware verification languages Hardware description languages Logic design SystemVerilog Debugging E Logic simulation VHDL Timing closure Electronic engineering Electronic design automation Digital electronics
7	Synopsys Professional Services Datasheet Physical Design Assistance At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:40:02 Timing closure Synopsys Physical design Design closure Tape-out Integrated circuits Signoff EDA database Electronic engineering Electronic design automation Electronic design
8	Synopsys Professional Services Datasheet Design Flow Deployment At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:39:43 Integrated circuits Electronic design Digital electronics Synopsys Timing closure Integrated circuit design Design flow Signoff EDA database Electronic engineering Electronics Electronic design automation
9	White Paper Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform February 2014 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:38 Timing closure Physical design Design closure Integrated circuit design Static timing analysis ECO Synopsys Signal integrity Design rule checking Electronic engineering Electronic design automation Signoff
10	Synopsys Professional Services Datasheet Tool and Methodology Consulting At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:40:16 Signoff SystemVerilog Power optimization EDA database Timing closure Electronic engineering Electronic design automation Synopsys