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Renau
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#	Item
11	Positional Adaptation of Processors: Application to Energy Reduction ∗ Michael C. Huang Jose Renau and Josep Torrellas Dept. of Electrical and Computer Engineering Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-04-01 22:17:30 Subroutines Cache Holism Source code University of Cambridge Computer Laboratory Call stack CPU cache Parameter Algorithm Software engineering Computing Computer programming
12	L1 Data Cache Decomposition for Energy Efficiency Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 11:58:14 Cache CPU cache Computer architecture Computing R10000 Computer hardware Central processing unit Computer memory
13	Energy Efficient Hybrid Wakeup Logic Michael Huang, Jose Renau, and Josep Torrellas University of Rochester, University of Illinois at Urbana-Champaign* Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-29 12:05:14 Science Academia Knowledge Digital electronics Register file Logic
14	Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation∗ Jose Renau† James Tuck Wei Liu Luis Ceze Karin Strauss Josep Torrellas † Dept. of Computer Engineering, University of Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-09-06 12:30:36 Central processing unit Parallel computing Classes of computers Microprocessors Superscalar Microarchitecture Speculative multithreading SPECint Coprocessor Computing Computer hardware Computer architecture
15	CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:10:17 Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering
16	Estimating Design Time for System Circuits Cyrus Bazeghi Francisco J. Mesa-Mart´ınez Brian Greskamp† Josep Torrellas† Jose Renau Dept. of Computer Engineering, University of California Santa Cruz http://masc.soe.uc Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-02-28 21:02:12 Electronics manufacturing Electronic design Integrated circuits Electrical engineering Printed circuit board Routing Integrated circuit design Surface-mount technology PCB Electronic engineering Electronics Electromagnetism
17	Energy-Efficient Hybrid Wakeup Logic Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2002-07-31 19:49:18 Parallel computing Classes of computers Central processing unit Superscalar Branch predictor Reduced instruction set computing Instruction set Very long instruction word Microarchitecture Computer architecture Computing Computer hardware
18	POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure ∗ Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau† and Josep Torrellas Department of Computer Science University of Illinois at Urbana Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-10-16 17:56:00 Parallel computing Compiler optimizations Computer architecture Software optimization Profiling Profilers Automatic parallelization Superscalar Fortran Computing Computer programming Software engineering
19	A Framework for Dynamic Energy Efficiency and Temperature Management Michael Huang , Jose Renau , Seung-Moon Yoo , and Josep Torrellas Department of Computer Science Department of Electrical and Computer Engineering Univ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 12:19:17 Cache Central processing unit Computer architecture Microprocessors CPU cache Multi-core processor Parallel computing Dynamic random-access memory Computer hardware Computing Computer memory
20	Josep Renau’s Futuro Trabajador del Comunismo An Emblematic Work of the Era of the Scientific-Technical Revolution in the German Democratic Republic1 Add to Reading List Source URL: www.essex.ac.uk Language: English - Date: 2013-12-16 06:54:33 Communism David Alfaro Siqueiros Mural East Germany Erich Honecker Mexican muralism Socialist Unity Party of Germany José Clemente Orozco Diego Rivera Visual arts Mexican people Eastern Bloc

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