Corey: An Operating System for Many Cores Silas Boyd-Wickizer∗ Haibo Chen† Rong Chen† Yandong Mao† Frans Kaashoek∗ Robert Morris∗ Aleksey Pesterev∗ Lex Stein‡ Ming Wu‡ Yuehua Dai◦ Yang Zhang∗ Zheng

Source URL: ipads.se.sjtu.edu.cn

• Computing
• Computer architecture
• Computer engineering
• Parallel computing
• Concurrent computing
• Manycore processors
• Central processing unit
• Multi-core processor
• Kernel
• Thread
• CPU cache
• Linux kernel

DSP APN502/APN504/APN508 MADE IN JAPAN Digital Signal Processor for γ-ray Spectroscopy

Source URL: www.techno-ap.com

Advanced  x86:   BIOS  and  System  Management  Mode  Internals   SMRAM  (System  Management  RAM)   Xeno  Kovah  &&  Corey  Kallenberg   LegbaCore,  LLC  

Source URL: opensecuritytraining.info

• Computer architecture
• Computing
• Computer engineering
• X86 architecture
• Rootkits
• System Management Mode
• IBM PC compatibles
• Central processing unit
• X86-64
• X86
• SMI
• Processor register

Monthly Report for August 2008 Contract No.: SP4705-07-C-0012 Funding Agency: Defense Logistics Agency - Defense Technical Information Center

Source URL: extract.cs.odu.edu

• Scripting languages
• Template processor
• Template

Template for Preparation of Papers for IEEE Sponsored Conferences & Symposia

Source URL: geneura.ugr.es

• Software
• Microsoft Office
• Piscataway
• New Jersey
• Bibliography
• IEEE style
• TIFF
• Microsoft Excel
• Institute of Electrical and Electronics Engineers
• Word processor
• HTML element
• Microsoft Word
• Page layout

Windows XP Supported Features on 4th Gen Intel Core Processor-based Products Ingredient 3rd Gen Windows XP

Source URL: www.dfi.com

REAL-TIME MUSICAL APPLICATIONS ON AN EXPERIMENTAL OPERATING SYSTEM FOR MULTI-CORE PROCESSORS Juan A. Colmenares1 , Ian Saxton1,2 , Eric Battenberg1,2 , Rimas Aviˇzienis1,2 , Nils Peters1,2,3 Krste Asanovi´c1,3 , John D

Source URL: www.ericbattenberg.com

• Concurrent computing
• Parallel computing
• Computing
• Computer programming
• Data parallelism
• Task parallelism
• Scheduling
• Thread
• Multi-core processor
• Instruction-level parallelism
• Work stealing
• Multithreading

MonetDB/X100: Hyper-Pipelining Query Execution Peter Boncz, Marcin Zukowski, Niels Nes CWI Kruislaan 413 Amsterdam, The Netherlands {P.Boncz,M.Zukowski,N.Nes}@cwi.nl

Source URL: www-db.cs.wisc.edu

• Central processing unit
• Relational database management systems
• Instruction set architectures
• Cross-platform software
• MonetDB
• Structured storage
• Column-oriented DBMS
• Pipeline
• CPU cache
• Optimizing compiler
• Vector processor
• Reduced instruction set computing

Institut für Technische Informatik und Kommunikationsnetze Computer Engineering and Networks Laboratory Prof. L. Thiele

Source URL: www.tik.ee.ethz.ch

• Parallel computing
• Manycore processors
• Reconfigurable computing
• Computer architecture
• Microprocessors
• Multi-core processor
• Massively parallel processor array
• Tilera
• Adapteva
• Benchmark
• TILE64
• CPU cache

Association Rule Mining with the Micron Automata Processor Ke Wang† , Yanjun Qi† , Jeffrey J. Fox‡ , Mircea R. Stan§ and Kevin Skadron† † Dept. of Comp. Sci., ‡ Dept. of Mater. Sci., § Dept. of Elec. & Comp

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