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Microarchitecture
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#	Item
131	Tradeoffs in Buffering Speculative Memory State for Thread-Level Speculation in Multiprocessors ´ GARZARAN ´ MAR´ıA JESUS Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-02-05 01:16:31 Central processing unit Computer memory Parallel computing Microarchitecture Process Circular buffer Reduced instruction set computing Cache Computing Computer hardware Computer architecture
132	Empowering Software Debugging Through Architectural Support for Program Rollback Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-07-29 18:41:35 Central processing unit Computer memory Computer errors Speculative execution CPU cache Kernel Debugging Microarchitecture Software bug Computing Computer architecture Computer hardware
133	Designing Hardware that Supports Cycle-Accurate Deterministic Replay Brian Greskamp, Smruti R. Sarangi, and Josep Torrellas Department of Computer Science, University of Illinois http://iacoma.cs.uiuc.edu Abstract Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-06-25 20:29:30 Computer buses Motherboard Central processing unit Digital electronics Microarchitecture Interrupt Front-side bus HyperTransport Itanium Computer hardware Computer architecture Electronic engineering
134	Tasking with Out-o Out of-Order o Order Spawn in of TLS Chip Multtiprocessors: Microarchitecture and Compilation Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-25 23:43:45 Intel Core Electronics Computing Electronic engineering Renau Microprocessor
135	Facelift: Hiding and Slowing Down Aging in Multicores∗ Abhishek Tiwari and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-09-13 00:18:06 Computer hardware Computer architecture Integrated circuits Microprocessors Electronic design Frequency scaling Microarchitecture Hot carrier injection CPU cache Electronic engineering Electronics Central processing unit
136	Scalable   Cache Miss Handling   For High MLP James Tuck, Luis Ceze, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-01-01 23:58:17 Computer engineering Computer memory Microprocessors CPU cache Cache Memory-level parallelism Runahead Intel Core Microarchitecture Computer architecture Computer hardware Central processing unit
137	The RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.0 Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovi´c CS Division, EECS Department, University of California, Berkeley Add to Reading List Source URL: riscv.org Language: English - Date: 2014-08-05 19:51:49 Instruction set X86 Microarchitecture Central processing unit ARM architecture Reduced instruction set computing 64-bit Very long instruction word IBM POWER Computer architecture Instruction set architectures DEC Alpha
138	Rebound: Scalable Checkpointing for Coherent Shared Memory Rishi Agarwal, Pranav Garg, and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,garg11,torrella}@illinois.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-04-01 11:24:25 Central processing unit Microprocessors Application checkpointing Computer memory Parallel computing CPU cache Multi-core processor AMD 10h Microarchitecture Computer architecture Computer hardware Computing
139	Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-04-04 17:00:54 Computing Microprocessors Threads Parallel computing CPU cache Computer memory Multithreading Microarchitecture Threading Computer hardware Computer architecture Central processing unit
140	Theme Feature . A Single-Chip Multiprocessor Add to Reading List Source URL: www-hydra.stanford.edu Language: English - Date: 1998-03-07 07:33:31 Parallel computing Central processing unit Microprocessors Threads Simultaneous multithreading Superscalar Multithreading Microarchitecture Multi-core processor Computing Computer architecture Computer hardware

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