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Out-of-order execution
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1	F ORESHADOW: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution Jo Van Bulck1 , Marina Minkin2 , Ofir Weisse3 , Daniel Genkin3 , Baris Kasikci3 , Frank Piessens1 , Mark Silberstein2 , Thom Add to Reading List Source URL: foreshadowattack.eu Language: English - Date: 2018-08-31 11:04:52 Computer architecture Computing Computer hardware Computer memory Cache Computer security X86 architecture Central processing unit Software Guard Extensions Meltdown CPU cache Spectre
2	Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution Revision 1.0 (August 14, 2018) Ofir Weisse3 , Jo Van Bulck1 , Marina Minkin2 , Daniel Genkin3 , Baris Kasikci3 , Frank Piessens Add to Reading List Source URL: foreshadowattack.eu Language: English - Date: 2018-08-31 11:04:51 Computer architecture Computing Computer hardware Computer memory Memory management Virtual memory X86 architecture Computer security Meltdown Translation lookaside buffer CPU cache Software Guard Extensions
3	Lecture Notes: Out-of-Order Processors Rajeev Balasubramonian October 13, 2007 Most modern high-performance processors today employ out-of-order execution. These notes cover the design of a microarchitecture style that i Add to Reading List Source URL: www.eng.utah.edu Language: English - Date: 2008-08-26 19:48:44
4	EN164: Design of Computing Systems Lecture 24: Processor / ILP 5 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:59 X86 architecture Central processing unit Parallel computing X86 Pentium Pro Superscalar MOV Out-of-order execution P6 Computer architecture Computer engineering Computing
5	Today’s Big Idea CS252 Graduate Computer Architecture Lecture 18: Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:51 Central processing unit Branch predictor Instruction set architectures Alpha 21264 Register renaming DEC Alpha CPU cache Out-of-order execution Re-order buffer Computer architecture Computer hardware Computer engineering
6	Code Reordering and Speculation Support for Dynamic Optimization Systems Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten, Wen-mei W. Hwu Center for Reliable and High-Performance Computing University of Illinois Urba Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:01 Out-of-order execution Electronics Very long instruction word Compiler optimization Instruction set Computer architecture Assembly languages Memory disambiguation Delay slot Computing Programming language implementation Explicitly parallel instruction computing
7	Late-Binding: Enabling Unordered Load-Store Queues Franziska Roesner x Simha Sethumadhavan x y x Joel S. Emer Add to Reading List Source URL: www.franziroesner.com Language: English - Date: 2009-10-21 14:03:34 Central processing unit Memory disambiguation CPU cache Microarchitecture Hazard Branch predictor Processor register Out-of-order execution DEC Alpha Computer architecture Computer hardware Computer engineering
8	Overcoming the Limitations of Conventional Vector Processors Christos Kozyrakis Electrical Engineering Department Stanford University Abstract Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 2003-03-27 17:31:06 Central processing unit Parallel computing Classes of computers Vector processor Instruction set DEC Alpha Alpha 21264 Vectorization Out-of-order execution Computer architecture Computing Computer hardware
9	MORRISON SECURITIES PTY LIMITED BEST EXECUTION POLICY This policy sets out the procedures to be followed to ensure that Morrison Securities Pty Limited (“Morrison”) complies with its obligations under the Corporation Add to Reading List Source URL: www.morrisonsecurities.com Language: English - Date: 2013-02-26 04:45:46 Financial regulation Australian Securities Exchange Economy of New South Wales Economy of Australia Best execution Order Financial markets Investment broker Stock market Financial economics Investment
10	IBM zNext – The 3rd Generation High Frequency Microprocessor Chip Chung-Lung (Kevin) Shum Senior Technical Staff Member, System z Processor Development, Systems & Technology Group, IBM Corp. Under NDA until Announceme Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:27:17 Out-of-order execution Z/Architecture Mainframe computer IBM zEnterprise System Smarter Planet Central processing unit Microcode Computer architecture IBM System z Server hardware