Digital signal processors

Results: 194



#Item
1® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO

® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO

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Source URL: www.hotchips.org

Language: English - Date: 2015-08-21 02:18:26
2BidSwitch DSP/Agency Seat Mapping Overview BidSwitch is an infrastructure layer that serves as a single integration point between SSPs and DSPs, providing our partners with an efficient and transparent way to manage acce

BidSwitch DSP/Agency Seat Mapping Overview BidSwitch is an infrastructure layer that serves as a single integration point between SSPs and DSPs, providing our partners with an efficient and transparent way to manage acce

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Source URL: www.bidswitch.com

Language: English - Date: 2016-07-18 07:18:12
3Chapter 1 CUSTOMIZABLE AND REDUCED HARDWARE MOTION ESTIMATION PROCESSORS Nuno Roma, Tiago Dias, Leonel Sousa Abstract

Chapter 1 CUSTOMIZABLE AND REDUCED HARDWARE MOTION ESTIMATION PROCESSORS Nuno Roma, Tiago Dias, Leonel Sousa Abstract

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Source URL: www.inesc-id.pt

Language: English - Date: 2005-11-28 09:20:12
4Microsoft Word - Vimicro_VC3809_PB_IPC_V1.0.doc

Microsoft Word - Vimicro_VC3809_PB_IPC_V1.0.doc

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Source URL: www.vimicro.com

Language: English - Date: 2014-12-05 01:06:52
5dsp_DBMD4_brochure_070316

dsp_DBMD4_brochure_070316

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Source URL: www.dspg.com

Language: English - Date: 2016-03-08 04:57:37
6dsp_Solution Portfolio-Tables_130316.indd

dsp_Solution Portfolio-Tables_130316.indd

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Source URL: www.dspg.com

Language: English - Date: 2016-03-13 06:23:44
7Domestic Russia Price List

Domestic Russia Price List

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Source URL: www.mlabsys.com

Language: English - Date: 2015-05-17 03:28:27
8Oblivious Algorithms for Multicores and Network of Processors  ? Rezaul Alam Chowdhury1 , Francesco Silvestri2 , Brandon Blakeley1 , and Vijaya Ramachandran1 1

Oblivious Algorithms for Multicores and Network of Processors ? Rezaul Alam Chowdhury1 , Francesco Silvestri2 , Brandon Blakeley1 , and Vijaya Ramachandran1 1

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Source URL: www.itu.dk

Language: English - Date: 2015-01-07 05:01:32
9Power-efficiency, Performance, Programmability: Architecture and Design in Bristol David May, Bristol University  David May

Power-efficiency, Performance, Programmability: Architecture and Design in Bristol David May, Bristol University David May

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Source URL: www.cs.bris.ac.uk

Language: English - Date: 2004-10-09 05:59:28