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#	Item
1	Microsoft Word - Aldec_HES-7_Febdocx Add to Reading List Source URL: www.avant-tek.com - Date: 2015-03-04 21:10:30
2	Product Line High-Performance Simulator for Mixed Language Designs IEEE VHDL, SystemVerilog, Verilog-AMS, SystemC/C/C++ Verification Ecosystem Add to Reading List Source URL: www.aldec.com Language: English - Date: 2015-07-31 14:44:56
3	CyberWorkBench® High-Level Synthesis and Verification by: SystemC High-Level Synthesis and Verification Add to Reading List Source URL: www.aldec.com Language: English - Date: 2013-08-07 16:44:00 Fabless semiconductor companies Hardware description languages Logic design Aldec Field-programmable gate array Xilinx High-level synthesis Altera SystemC Electronic engineering Digital electronics Electronic design automation
4	RTAX_DatasheetPP1_Rev2012.02 Add to Reading List Source URL: www.aldec.com Language: English - Date: 2014-09-11 15:12:23
5	HES-DVM™ HW/SW Validation Platform Hybrid Verification Platform HES-DVMTM is a Hybrid Verification and Validation Platform for Hardware and Software developers of SoC and ASIC designs up to 144M ASIC gates. Utilizing Add to Reading List Source URL: www.aldec.com Language: English - Date: 2015-02-02 17:14:32 Hardware verification languages Aldec Logic design Hardware emulation Hardware description languages Field-programmable gate array Joint Test Action Group Mentor Graphics Application-specific integrated circuit Electronic engineering Electronic design automation Digital electronics
6	ALINT-PRO-CDC™ CDC Verification Static Structural Verification Clock Domain Crossing Verification ALINT-PRO-CDC™ is a design verification solution from Aldec which enables verification of clock domain crossings and Add to Reading List Source URL: www.aldec.com Language: English - Date: 2015-05-05 17:04:02 Hardware verification languages Aldec Electronic design SystemVerilog E Clock domain crossing Verilog VHDL Functional verification Electronic engineering Electronic design automation Hardware description languages
7	Riviera-PRO™ Advanced Verification Verification Platform Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench pro Add to Reading List Source URL: www.aldec.com Language: English - Date: 2015-05-05 17:04:52 Hardware verification languages Aldec Logic design SystemVerilog Verilog SystemC VHDL E Simulink Electronic engineering Hardware description languages Electronic design automation
8	ProductLinePP1_Rev2013.04b Add to Reading List Source URL: www.aldec.com Language: English - Date: 2013-11-20 17:35:33 Aldec Electronic engineering Hardware description languages Electronic design automation
9	DO-254_BrochurePP1_Rev2012.02 Add to Reading List Source URL: www.aldec.com Language: English - Date: 2014-09-10 19:05:25 Electronic design Integrated circuits Fabless semiconductor companies Aldec Embedded systems Logic design Field-programmable gate array Integrated circuit design DO-254 Electronic engineering Electronics Digital electronics
10	PDF Document Add to Reading List Source URL: www.aldec.com Language: English - Date: 2015-02-02 14:11:43 Electronics Aldec Systems engineering Requirements traceability Traceability Requirement Change impact analysis Field-programmable gate array Application-specific integrated circuit Software requirements Electronic engineering Technology