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Register-transfer level
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1	C vs. VHDL: Benchmarking CAESAR Candidates Using High-‐Level Synthesis and Register-‐Transfer Level Methodologies Ekawat Homsirikamol, Wi Add to Reading List Source URL: www1.spms.ntu.edu.sg Language: English - Date: 2015-10-04 23:56:37
2	Formal Verification for High-Assurance Behavioral Synthesis Sandip Ray1 , Kecheng Hao2 , Yan Chen3 , Fei Xie2 , and Jin Yang4 1 Department of Computer Sciences, University of Texas at Austin, Austin, TX 78712 Add to Reading List Source URL: www.mpi-sws.org Language: English - Date: 2011-07-23 03:32:42 Electronic engineering Electronic design automation Design Formal methods Electronics Electronic design Formal equivalence checking Formal verification High-level synthesis Integrated circuit design Register-transfer level Invariant
3	Microsoft Word - CummingsSNUG2003Boston_Resets_rev1_3.doc Add to Reading List Source URL: www.sunburst-design.com Language: English - Date: 2004-07-20 21:15:36 Hardware description languages Digital electronics VHDL Verilog Flip-flop Counter Reset Metastability in electronics Sequential logic Register-transfer level
4	Automatic Validation of Code-Improving Transformations on Low-Level Program Representations ∗ Robert van Engelen, David Whalley, and Xin Yuan Department of Computer Science, Florida State University, Tallahassee, FL 32 Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2004-03-02 08:35:51 Compiler Compiler construction ARM architecture NOP GNU Compiler Collection Register-transfer level E1 Algorithm Software Computing Programming language implementation
5	Designing with VHDL FPGA 1 LANG11000-ILT (v1.0) Course Specification Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2014-11-12 18:34:24 VHDL Digital electronics Field-programmable gate array Logic synthesis Xilinx Register-transfer level Electronic engineering Hardware description languages Electronic design automation
6	Yosys Open SYnthesis Suite Clifford Wolf (http://www.clifford.at/yosys/) Clifford Wolf http://www.clifford.at/yosys/ Add to Reading List Source URL: www.clifford.at Language: English - Date: 2015-02-09 07:25:30 Hardware description languages Logic design Technical communication Verilog Register-transfer level VHDL Field-programmable gate array Application-specific integrated circuit Logic gate Electronic engineering Electronic design automation Digital electronics
7	Yosys Manual Clifford Wolf Abstract Most of today’s digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools. Add to Reading List Source URL: www.clifford.at Language: English - Date: 2015-02-09 07:25:28 Electronic design Digital electronics Verilog Logic synthesis VHDL Field-programmable gate array High-level synthesis Application-specific integrated circuit Register-transfer level Electronic engineering Electronic design automation Hardware description languages
8	ALINT™ Design Rule Checking Methodology Detects Design Flaws Early Aldec’s ALINT™ design analysis tool identifies critical design Add to Reading List Source URL: www.aldec.com Language: English - Date: 2014-09-11 15:01:15 Integrated circuits Aldec Electronic design VHDL Verilog Field-programmable gate array Application-specific integrated circuit Integrated circuit design Register-transfer level Electronic engineering Electronic design automation Hardware description languages
9	Implementing an Instruction Set David E. Culler CS61CL Oct 28, 2009 Lecture 9 Add to Reading List Source URL: inst.eecs.berkeley.edu Language: English - Date: 2009-10-28 23:04:23 Central processing unit Digital electronics Electronic design Datapath Register-transfer level Flip-flop Electronic engineering Electronic design automation Electronics
10	PDF Document Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2011-04-14 06:00:26 Electronic design Hardware verification languages SystemC Verilog Register-transfer level High-level synthesis Logic synthesis VHDL Integrated circuit design Electronic engineering Electronic design automation Hardware description languages