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Branch misprediction
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#	Item
1	Reducing the Cost of Conditional Transfers of Control by Using Comparison Specifications William Kreahling Western Carolina University Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2006-04-21 21:30:19 Branch predictor Branch misprediction Assembly languages Instruction set Branch predication Compiler optimization ARM architecture Processor register Classic RISC pipeline Computer architecture Central processing unit Instruction set architectures
2	Boolean Formula-based Branch Prediction for Future Technologies Daniel A. Jim´enez Dept. of Computer Sciences The University of Texas at Austin Austin, TX 78712 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:47:57 Branch predictor Boolean algebra Alpha 21264 CPU cache Branch misprediction Lookup table Boolean function Boolean circuit Computing Computer architecture Computer hardware
3	Parallel Architectures and Compilation Techniques PACT 2001 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2001-10-11 10:17:25 Central processing unit Parallel computing Branch predication Instruction set Branch misprediction Superscalar Computer architecture Computing Computer engineering
4	Lecture 5: VLIW, Software Pipelining, and Limits to ILP Professor David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-02-06 15:14:03 Computer engineering Register renaming Branch misprediction Prediction R10000 Loop unwinding Branch Lookup table DEC Alpha Computing Computer architecture Branch predictor
5	ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing ∗ Smruti R. Sarangi, Wei Liu, Josep Torrellas, and Yuanyuan Zhou University of Illinois at Urbana-Champaign {sarangi,liuw Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-09-06 12:30:36 Computing CPU cache Data dependency Branch misprediction Branch predictor Instruction set Memory disambiguation Computer hardware Central processing unit Computer engineering
6	Microsoft PowerPoint - reslice4 [Compatibility Mode] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-25 19:05:13 Computer architecture Branch misprediction Slicing Computing
7	Microsoft PowerPoint - Finley Add to Reading List Source URL: www.nmspacegrant.com Language: English - Date: 2011-04-26 18:23:38 CPU cache Cache Computer memory Software optimization Profiling Branch misprediction Simulation FP Computer engineering Computer hardware Computing Central processing unit
8	Levo - A Scalable Processor With High IPC Add to Reading List Source URL: www.jilp.org Language: English - Date: 2003-08-25 17:41:38 Central processing unit Instruction set architectures Branch predication Instruction set Tomasulo algorithm Branch misprediction Microarchitecture DEC Alpha Operand forwarding Computer architecture Computer hardware Computing
9	AN ALTERNATIVE TO BRANCH PREDICTION: P R E - C O M P U T E D BRANCHES Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2008-11-17 09:44:18 Central processing unit Branch predictor Assembly languages Hazard Branch misprediction Instruction set CPU cache Addressing mode Delay slot Computer architecture Computer hardware Computer engineering
10	BRANCH PREDICTION: A CRITICISM AND A NOVEL SCHEME Lucian N. VINTAN, Adrian FLOREA “L. Blaga” University of Sibiu, Department of Computer Science, Str. E. Cioran, No. 4, Sibiu-2400, ROMANIA, E-mail: [removed] Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-05-17 01:48:52 Computer engineering Branch predictor CPU cache Prediction Branch misprediction RSA Microarchitecture Computer architecture Computer hardware Central processing unit