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Task state segment
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#	Item
1	1 FROM RING3 TO RING0: EXPLOITING THE XEN X86 INSTRUCTION EMULATOR Andrei Vlad Luțaș Bitdefender Add to Reading List Source URL: labs.bitdefender.com Language: English - Date: 2016-01-22 04:06:36 Computer architecture Computing X86 architecture Interrupts X86 instructions Memory management Interrupt descriptor table Task state segment Global Descriptor Table Interrupt flag X86 Interrupt
2	The Page-Fault Weird Machine: Lessons in Instruction-less Computation Julian Bangert, Sergey Bratus, Rebecca Shapiro, Sean W. Smith Abstract not unique to either the x86 Memory Management Unit Add to Reading List Source URL: www.cs.dartmouth.edu Language: English - Date: 2013-09-11 09:08:25 Virtual memory Memory management Central processing unit Task state segment Global Descriptor Table X86 assembly language Protected mode Interrupt descriptor table Memory management unit Computer architecture X86 architecture Interrupts
3	Windows 2000/XP and the IOMAP Accessing IO-Ports under Windows 2000/XP Copyright © 2002 SYBERA Whitepaper No[removed] On of the most surprising issue is how Windows 2000/XP denies accessing IO-Port addresses. Add to Reading List Source URL: www.sybera.de Language: English - Date: 2013-03-22 02:11:06 Device driver Windows NT Windows XP INF file Task state segment Windows Protected mode Windows Driver Model Architecture of Windows NT Microsoft Windows Computer architecture Software
4	GDT and LDT in Windows kernel vulnerability exploitation Matthew “j00ru” Jurczyk and Gynvael Coldwind, Hispasec Abstract Add to Reading List Source URL: vexillium.org Language: English Global Descriptor Table Local Descriptor Table Protected mode X86 memory segmentation Task state segment Call gate Memory protection Segment descriptor Context switch Computer architecture X86 architecture Memory management
5	ELA Formative Assessment Task Checklist Task Segment Effective Task Characteristics Checklist Grade Level The grade level is appropriate for the Common Core Standard and corresponding task. CCSS The Common Core State S Add to Reading List Source URL: www.justreadflorida.com Language: English - Date: 2014-02-04 15:17:15 Educational psychology Evaluation Academia Educational technology Rubric Formative assessment E-learning Assessment for Learning Education Evaluation methods Knowledge
6	Machine check handling on Linux http://www.firstfloor.org/~andi/mce.pdf Andi Kleen, SuSE Labs [removed] What is a machine check? Add to Reading List Source URL: halobates.de Language: English - Date: 2008-03-31 04:13:52 Machine Check Exception Machine check architecture Kernel panic Non-maskable interrupt Kernel Linux kernel Opteron Segmentation fault Task state segment Computing Computer errors Computer architecture
7	Machine check handling on Linux http://www.firstfloor.org/~andi/mce.pdf Andi Kleen, SuSE Labs [removed] What is a machine check? Add to Reading List Source URL: www.halobates.de Language: English - Date: 2008-03-31 04:13:52 Machine Check Exception Machine check architecture Kernel panic Non-maskable interrupt Kernel Linux kernel Opteron Segmentation fault Task state segment Computing Computer errors Computer architecture
8	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:24:55 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86
9	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: support.amd.com Language: English - Date: 2013-11-01 16:14:30 X86 Interrupt descriptor table Task state segment Global Descriptor Table Protected mode CPUID Processor register Context switch INT Computer architecture X86 architecture Control register
10	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:25:06 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86