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Segment descriptor
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#	Item
1	1 FROM RING3 TO RING0: EXPLOITING THE XEN X86 INSTRUCTION EMULATOR Andrei Vlad Luțaș Bitdefender Add to Reading List Source URL: labs.bitdefender.com Language: English - Date: 2016-01-22 04:06:36 Computer architecture Computing X86 architecture Interrupts X86 instructions Memory management Interrupt descriptor table Task state segment Global Descriptor Table Interrupt flag X86 Interrupt
2	67. Proc. AFIPS 1966 Spring Joint Cornpnt. Conf., Vol. 28. Spartan Books, New York, ppGL Add to Reading List Source URL: www.eecs.harvard.edu Language: English Memory management Multics Burroughs large systems X86 architecture Virtual memory Memory segmentation Pointer Relocation Memory address Subroutine Segment descriptor X86 memory segmentation
3	The Page-Fault Weird Machine: Lessons in Instruction-less Computation Julian Bangert, Sergey Bratus, Rebecca Shapiro, Sean W. Smith Abstract not unique to either the x86 Memory Management Unit Add to Reading List Source URL: www.cs.dartmouth.edu Language: English - Date: 2013-09-11 09:08:25 Virtual memory Memory management Central processing unit Task state segment Global Descriptor Table X86 assembly language Protected mode Interrupt descriptor table Memory management unit Computer architecture X86 architecture Interrupts
4	O PROTECTION IN AN INFORMATION PROCESSING UTILITY Add to Reading List Source URL: www.multicians.org Language: English - Date: 2012-11-08 16:33:53 X86 architecture Central processing unit Ring Multics Operating system Segment descriptor General protection fault Protected mode Computer architecture Computing Memory management
5	GDT and LDT in Windows kernel vulnerability exploitation Matthew “j00ru” Jurczyk and Gynvael Coldwind, Hispasec Abstract Add to Reading List Source URL: vexillium.org Language: English Global Descriptor Table Local Descriptor Table Protected mode X86 memory segmentation Task state segment Call gate Memory protection Segment descriptor Context switch Computer architecture X86 architecture Memory management
6	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:24:55 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86
7	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: support.amd.com Language: English - Date: 2013-11-01 16:14:30 X86 Interrupt descriptor table Task state segment Global Descriptor Table Protected mode CPUID Processor register Context switch INT Computer architecture X86 architecture Control register
8	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:25:06 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86
9	PDF Document Add to Reading List Source URL: microsym.com Language: English - Date: 2006-03-14 16:55:04 Interrupts Central processing unit X86 instructions Memory management Interrupt descriptor table Control register Task state segment Interrupt flag INT Computer architecture Computing X86 architecture
10	PDF Document Add to Reading List Source URL: support.amd.com Language: English - Date: 2013-05-08 17:06:40 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86

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