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51	UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C[removed]FORM 10-K As filed on December 17, 2010 and amended on February 9, 2011 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-24 17:15:58 Hillsboro Oregon Synopsys Digital electronics Mentor Graphics Magma Design Automation Cadence Design Systems Logic synthesis SystemVerilog Signoff Electronic engineering Electronic design automation Electronic design
52	SystemVerilog 3.1a Language Reference Manual Add to Reading List Source URL: www.eda.org Language: English - Date: 2004-05-13 18:43:42 Hardware description languages SystemVerilog Accellera Verilog Phil Moorby E Parallel Random Access Machine Electronic engineering Electronic design automation Hardware verification languages
53	Synopsys Professional Services Datasheet Tool and Methodology Consulting At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:40:16 Signoff SystemVerilog Power optimization EDA database Timing closure Electronic engineering Electronic design automation Synopsys
54	Synopsys Professional Services Datasheet SoC Integration & Verification At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:40:10 Hillsboro Oregon Synopsys SystemVerilog Physical design Functional verification E OpenVera Virtual Socket Interface Alliance Electronic engineering Electronic design automation Hardware verification languages
55	Datasheet VCS Functional Verification Choice of Leading SoC Design Teams Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:41:22 Hardware description languages SystemVerilog OpenVera E Functional verification Synopsys Open Verification Methodology Verilog Logic simulation Electronic engineering Electronic design automation Hardware verification languages
56	Datasheet Formality and Formality Ultra Equivalence Checking for DC Ultra and Design Compiler Graphical Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 15:15:30 Formal methods Physical design SystemVerilog Synopsys Formal verification Verilog Formal equivalence checking Signoff Electronic engineering Electronic design automation Hardware description languages
57	Datasheet Verdi3 Automated Debug System Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-01-20 19:15:21 Hardware verification languages Hardware description languages Logic design SystemVerilog Debugging E Logic simulation VHDL Timing closure Electronic engineering Electronic design automation Digital electronics
58	Datasheet Synphony C Compiler High-Level Synthesis from C/C++ to RTL Overview Add to Reading List Source URL: www.synopsys.com Language: English High-level synthesis Logic synthesis SystemVerilog Synopsys Verilog Clock gating Field-programmable gate array Catapult C Compiler Electronic engineering Electronic design automation Hardware description languages
59	Datasheet Synphony C Compiler High-Level Synthesis from C/C++ to RTL Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:31:02 High-level synthesis Logic synthesis SystemVerilog Synopsys Verilog Clock gating Field-programmable gate array Catapult C Compiler Electronic engineering Electronic design automation Hardware description languages
60	Datasheet Synplify Pro Fast, High-Performance FPGA Synthesis Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-12 14:38:42 Electronic design Field-programmable gate array Logic synthesis Synopsys High-level synthesis VHDL SystemVerilog Verilog Aldec Electronic engineering Hardware description languages Electronic design automation