| Document Date: 2014-11-07 14:41:22
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Company Register Abstraction Layer / VCS / Synopsys Inc. / Complete Assertion Technologies / / Country United States / / IndustryTerm report management / Web-based UI / native assertion technology / automated infrastructure management / assertion technologies / extensible infrastructure / multicore technology / integrated management solution / verification solution / methodology applications / diagnostic tools / constraint expression convergence technology / register and protocol / functional verification solution / bus protocols / formal property verification built-in coverage technology / project goals tools / / Person Shu (Shutdown) Shu / / Position Architect / Verification Planner / Execution Manager / Accellera Planner / Full Tcl scripting Annotated source Automated driver / back Execution Manager / planner / OVM Planner / / Product Synopsys Verification IP / / ProgrammingLanguage HTML / Tcl / Verilog / C++ / / Technology semiconductor / API / GPS / HTML / VHDL / native assertion technology / formal property verification built-in coverage technology / Echo constraint expression convergence technology / Verilog / multicore technology / bus protocols / assertion technologies / DLP / simulation / GUI / / URL http /
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Datasheet VCS Functional Verification Choice of Leading SoC Design Teams Overview