Formal equivalence checking - PDFSEARCH.IO - Document Search Engine

Formal equivalence checking
Results: 14

#	Item
1	Continued Relevance of Bit-Level Verification Research R. Brayton, N. Een, A. Mishchenko Berkeley Verification and Synthesis Research Center EECS Dept., University of California, Berkeley Introduction Add to Reading List Source URL: fm.csl.sri.com Language: English - Date: 2010-10-30 02:14:08 Theoretical computer science Formal methods Logic in computer science Electronic design automation NP-complete problems Boolean algebra Boolean satisfiability problem Solver Formal equivalence checking Formal verification Model checking Uclid
2	Formal Verification for High-Assurance Behavioral Synthesis Sandip Ray1 , Kecheng Hao2 , Yan Chen3 , Fei Xie2 , and Jin Yang4 1 Department of Computer Sciences, University of Texas at Austin, Austin, TX 78712 Add to Reading List Source URL: www.mpi-sws.org Language: English - Date: 2011-07-23 03:32:42 Electronic engineering Electronic design automation Design Formal methods Electronics Electronic design Formal equivalence checking Formal verification High-level synthesis Integrated circuit design Register-transfer level Invariant
3	Digital System Microprocessor project Fabrice Ben Hamouda, Yoann Bourse, Hang Zhou : Semestre 1 Add to Reading List Source URL: www.normalesup.org Language: English Electronic engineering Electronic design automation Digital electronics Design Netlist Adder Application-specific integrated circuit Logic gate Formal equivalence checking Standard cell
4	White Paper Understanding DO-254 Compliance for the Verification of Airborne Digital Hardware October 2009 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-05-07 08:15:40 Integrated circuits Formal methods DO-254 Functional verification Logic simulation Electronic design automation Integrated circuit design Formal equivalence checking Synopsys Electronic engineering Electronics Electronic design
5	Datasheet Formality and Formality Ultra Equivalence Checking for DC Ultra and Design Compiler Graphical Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 15:15:30 Formal methods Physical design SystemVerilog Synopsys Formal verification Verilog Formal equivalence checking Signoff Electronic engineering Electronic design automation Hardware description languages
6	VIRAM-1 Vector Datapath University of California, Berkeley Joseph Gebis Description Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 2000-01-20 23:40:07 Integrated circuits Electronic design Circuit extraction Application-specific integrated circuit Verilog Adder Datapath Standard cell Formal equivalence checking Electronic engineering Electronics Electronic design automation
7	better health through better communication www.mhcs.health.nsw.gov.au “CAN WE JUST CHECK IT?” Guidelines for Checking of Health/Medical Translations Add to Reading List Source URL: www.mhcs.health.nsw.gov.au Language: English - Date: 2014-02-18 23:47:46 Linguistics Translation Knowledge Communication Machine translation National Accreditation Authority for Translators and Interpreters Dynamic and formal equivalence Translation memory EN 15038 Science Translation studies Computer-assisted translation
8	Combinational Techniques for Sequential Equivalence Checking Hamid Savoj1 David Berthelot1 Alan Mishchenko2 Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2010-03-23 04:39:57 Digital electronics Formal methods Logic in computer science Automata theory Formal equivalence checking Combinational logic Sequential logic Automatic test pattern generation NC Theoretical computer science Electronic engineering Applied mathematics
9	Improvements to Combinational Equivalence Checking Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-08-09 21:17:37 Formal methods Logic in computer science NP-complete problems And-inverter graph Diagrams Boolean satisfiability problem Satisfiability Logic synthesis Automatic test pattern generation Electronic engineering Theoretical computer science Electronic design automation
10	White Paper Understanding DO-254 Compliance for the Verification of Airborne Digital Hardware October 2009 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:44:09 Integrated circuits Formal methods DO-254 Functional verification Logic simulation Electronic design automation Integrated circuit design Formal equivalence checking Synopsys Electronic engineering Electronics Electronic design

UPDATE