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#	Item
691	SHA-3 Conference, March 2012,SHA-3 Conference, March 2012, Lessons Learned from Designing a 65nm ASIC for Third Round SHA-3 Candidates Add to Reading List Source URL: csrc.nist.gov Language: English - Date: 2012-05-21 15:44:02 Electronic design automation Application-specific integrated circuit Standard cell ETH Zurich Field-programmable gate array Synopsys Throughput VHDL Mentor Graphics Electronic engineering Electronics Integrated circuits
692	Datasheet VCS AMS Mixed-Signal Verification Solution Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-03-06 15:46:48 Verilog-AMS SystemVerilog Verilog-A Verilog Synopsys SystemC Functional verification E System on a chip Electronic engineering Hardware description languages Electronic design automation
693	White Paper Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform February 2014 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:38 Timing closure Physical design Design closure Integrated circuit design Static timing analysis ECO Synopsys Signal integrity Design rule checking Electronic engineering Electronic design automation Signoff
694	Success Story Synopsys and Altera Altera’s SoC FPGA Virtual Target Enables Early Software Development and High Debug Productivity Add to Reading List Source URL: www.synopsys.com Language: English Fabless semiconductor companies Hillsboro Oregon Synopsys Field-programmable gate array Altera Simulation Embedded system Prototype Joint Test Action Group Electronic engineering Technology Electronics
695	PeP Testimonial Etron Achieves First-Silicon Success of USB3.0 SoC Using Synopsys Proven Solutions “By consolidating on Synopsys as our primary EDA partner, Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-12-01 10:15:55 Synopsys SystemC Digital electronics Electronic engineering Electronic design automation Hillsboro Oregon
696	White Paper Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks November 2011 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:37:36 Physics Electromigration Power network design Integrated circuit design Current density Reliability Physical design EM Current crowding Electronic engineering Electronic design automation Electromagnetism
697	Synopsys Flow – Cadence Flow RTL Logic Synthesis Floorplanning Add to Reading List Source URL: www.europractice-ic.com - Date: 2013-07-22 09:48:11
698	Synopsys Flow – Cadence Flow RTL Logic Synthesis Floorplanning Add to Reading List Source URL: www.europractice-ic.com - Date: 2013-07-22 09:48:11
699	Stacy D. Doss 9009 N R.R. 620 #301 [removed] www.linkedin.com/in/stacydoss Austin, TX[removed]9438 home[removed]cell Add to Reading List Source URL: 3monkeyweb.com Language: English - Date: 2013-07-03 12:55:23 Scripting languages Computing platforms Perl OpenAccess JavaScript Bugzilla Tcl Linux Synopsys Computing Software Cross-platform software
700	Equivalence Checking for Timing Constraints Subramanyam Sripada March 6, 2014 Add to Reading List Source URL: tauworkshop.com Language: English - Date: 2014-04-28 21:48:00 Burroughs MCP Software Electronic engineering Hardware description languages Computing Hillsboro Oregon Synopsys CLOCK

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