Processor design

Results: 274



#Item
1LOW-POWER PROCESSOR DESIGN  Ricardo E. Gonzalez Technical Report No. CSL-TR

LOW-POWER PROCESSOR DESIGN Ricardo E. Gonzalez Technical Report No. CSL-TR

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Source URL: www-vlsi.stanford.edu

Language: English - Date: 2009-05-29 13:24:27
    2Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect Tung Thanh Hoang, Ulf J¨almbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Sj¨alander, and Per Larsson-Edefors VLSI Resear

    Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect Tung Thanh Hoang, Ulf J¨almbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Sj¨alander, and Per Larsson-Edefors VLSI Resear

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    Source URL: www.sjalander.com

    Language: English - Date: 2012-05-31 04:43:15
      3Super-Scalar Processor Design William M. Johnson Technical Report No. CSL-TRJune 1989 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science

      Super-Scalar Processor Design William M. Johnson Technical Report No. CSL-TRJune 1989 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science

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      Source URL: www-vlsi.stanford.edu

      Language: English - Date: 2009-05-29 13:24:49
        4THE DESIGN SPACE OF REGISTER RENAMING TECHNIQUES TO BOOST PROCESSOR AND SYSTEM PERFORMANCE, VIRTUALLY ALL RECENT SUPERSCALARS RENAME REGISTERS.  Dezsö Sima

        THE DESIGN SPACE OF REGISTER RENAMING TECHNIQUES TO BOOST PROCESSOR AND SYSTEM PERFORMANCE, VIRTUALLY ALL RECENT SUPERSCALARS RENAME REGISTERS. Dezsö Sima

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        Source URL: www.eecs.umich.edu

        - Date: 2016-09-06 09:27:52
          5A CORPORATE HOUSEHOLDING KNOWLEDGE PROCESSOR TO IMPROVE DATA QUALITY  41 The Design and Implementation of a Corporate Householding Knowledge

          A CORPORATE HOUSEHOLDING KNOWLEDGE PROCESSOR TO IMPROVE DATA QUALITY 41 The Design and Implementation of a Corporate Householding Knowledge

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          Source URL: mitiq.mit.edu

          - Date: 2006-04-03 14:43:43
            6Programming for Future 3D Architectures with Manycore  Introduction The shift from Systems-on-Chip (SoC) to manycore architectures brings new hardware and software challenges ranging from seamless integration of processo

            Programming for Future 3D Architectures with Manycore Introduction The shift from Systems-on-Chip (SoC) to manycore architectures brings new hardware and software challenges ranging from seamless integration of processo

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            Source URL: www.pro3d.eu

            Language: English - Date: 2011-06-27 05:55:03
            71  Underdesigned and Opportunistic Computing in Presence of Hardware Variability Puneet Gupta1 , Member, IEEE, Yuvraj Agarwal2 , Member, IEEE, Lara Dolecek1 , Member, IEEE, Nikil Dutt6 , Fellow, IEEE, Rajesh K. Gupta2 ,

            1 Underdesigned and Opportunistic Computing in Presence of Hardware Variability Puneet Gupta1 , Member, IEEE, Yuvraj Agarwal2 , Member, IEEE, Lara Dolecek1 , Member, IEEE, Nikil Dutt6 , Fellow, IEEE, Rajesh K. Gupta2 ,

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            Source URL: mesl.ucsd.edu

            Language: English - Date: 2012-09-17 19:39:16
            8Design of Embedded Real Time Video Monitoring System Based on ARM11 Processor. Haseeba M.Tech (Embedded Systems) Department of ECE

            Design of Embedded Real Time Video Monitoring System Based on ARM11 Processor. Haseeba M.Tech (Embedded Systems) Department of ECE

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            Source URL: www.ijmetmr.com

            Language: English - Date: 2015-01-08 07:05:18
            9Design Issues in Parallel Array Languages for Shared Memory ! James Brodman1 , Basilio B. Fraguela2 , Mar´ıa J. Garzar´an1 , and David Padua1 1  University of Illinois at Urbana-Champaign, Dept. of Computer Science

            Design Issues in Parallel Array Languages for Shared Memory ! James Brodman1 , Basilio B. Fraguela2 , Mar´ıa J. Garzar´an1 , and David Padua1 1 University of Illinois at Urbana-Champaign, Dept. of Computer Science

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            Source URL: polaris.cs.uiuc.edu

            Language: English - Date: 2008-06-04 16:32:10
            10Term-Level Verification of a Pipelined CISC Microprocessor Randal E. Bryant December, 2005 CMU-CS

            Term-Level Verification of a Pipelined CISC Microprocessor Randal E. Bryant December, 2005 CMU-CS

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            Source URL: www.cs.cmu.edu

            Language: English - Date: 2006-01-09 17:18:43