Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor 4th Workshop on Network Calculus (WoNeCa-4) Marc Boyer (ONERA) Benoˆıt Dupont de Dinechin (Kalray) Amaury Graillat (Verimag, Karla

Source URL: disco.cs.uni-kl.de

Network Programmability: A holistic perspective Giuseppe Bianchi CNIT / University of Roma Tor Vergata Credits to: Wireless MAC processor

Source URL: www.beba-project.eu

Timing Analysis for Sensor Network Nodes of the Atmega Processor Family ∗ Sibin Mohan1 , Frank Mueller1 , David Whalley2 and Christopher Healy3 1 Dept. of Computer Science, Center for Embedded Systems Research, North C

Source URL: moss.csc.ncsu.edu

The Architecture of PIER: an Internet-Scale Query Processor Ryan Huebsch, Brent Chun, Joseph M. Hellerstein, Boon Thau Loo, Petros Maniatis, Timothy Roscoe, Scott Shenker, Ion Stoica and Aydan R. Yumerefendi UC Berkeley

Source URL: www-db.cs.wisc.edu

• Distributed data storage
• Computing
• Concurrent computing
• Distributed computing
• Distributed hash table
• Chord
• Koorde
• Gnutella
• Peer-to-peer
• Overlay network
• Routing
• Prefix hash tree

Advisory FIN-2012-A010 Issued: October 22, 2012 Subject: Risk Associated with Third-Party Payment Processors The Financial Crimes Enforcement Network (FinCEN) is issuing this Advisory to provide guidance to financial ins

Source URL: www.fincen.gov

• Economy
• Money
• Finance
• Payment systems
• Tax evasion
• Terrorism
• Financial regulation
• Money laundering
• Payment processor
• Financial Crimes Enforcement Network
• Bank Secrecy Act
• Suspicious activity report

Jet Propulsion Laboratory! California Institute of Technology! Digital Backend for JPL Deep Space Communications Complex VLBI Processor Casper Workshop 2010

Source URL: casper.berkeley.edu

• Radio astronomy
• California
• Jet Propulsion Laboratory
• La Caada Flintridge
• California
• NASA Deep Space Network
• Very-long-baseline interferometry
• JPL
• Greater Los Angeles Area
• Astronomy

∗ Taming the IXP Network Processor Lal George Network Speed Technologies, Inc

Source URL: people.cs.uchicago.edu

• Compiler optimizations
• Computing
• Central processing unit
• Operations research
• Computer engineering
• Computer hardware
• Computer architecture
• Processor register
• Register allocation
• Static single assignment form
• Integer programming
• CPU cache

Packet Transactions: High-Level Programming for Line-Rate Switches Anirudh Sivaraman¶ , Alvin Cheung‡ , Mihai Budiu§ ∗, Changhoon Kim† , Mohammad Alizadeh¶ , Hari Balakrishnan¶ , George Varghese++ , Nick McKeow

Source URL: sandcat.cs.washington.edu

• Computing
• Computer networking
• Packet processing
• Transmission Control Protocol
• Forwarding plane
• Fair queuing
• Network processor
• P4
• NetFlow
• Queuing delay
• Router
• Network switch

NESUS IC1305 Network for Sustainable Ultrascale Computing

Source URL: www.inesc-id.pt

• Computing
• Parallel computing
• Computer architecture
• GPGPU
• Graphics hardware
• High-definition television
• Video compression
• General-purpose computing on graphics processing units
• Graphics processing unit
• Multi-core processor
• Tegra
• Fermi

Microsoft Word - MEDEA2008-cfp_allineato.doc

Source URL: garga.iet.unipi.it

• Computing
• Concurrent computing
• Parallel computing
• Computer memory
• Computer architecture
• Microprocessors
• Electronic design automation
• Network on a chip
• Transactional memory
• Multi-core processor
• Very long instruction word
• Multiprocessing