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Microarchitecture
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#	Item
221	PDF Document Add to Reading List Source URL: media.wiley.com Language: English - Date: 2008-08-13 05:04:02 Central processing unit Microprocessors Parallel computing Classes of computers Multi-core processor Microarchitecture CPU cache Compiler optimization Processor register Computer hardware Computer architecture Computing
222	Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs Christopher W. Fletcher†∗, Ling Ren† , Xiangyao Yu† , Marten Van Dijk‡ , Omer Khan‡ , Srinivas D Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2014-01-23 18:47:27 CPU cache Dynamic random-access memory Synchronous dynamic random-access memory Side channel attack Microarchitecture DIMM CAS latency Static random-access memory SDRAM latency Computer memory Computer hardware Computing
223	A Secure Processor Architecture for Encrypted Computation on Untrusted Programs Christopher Fletcher Marten van Dijk Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2012-10-19 22:35:51 Computer engineering Computer memory Cache CPU cache Microprocessors Microarchitecture Computer hardware Central processing unit Computer architecture
224	IEEE COMPUTER ARCHITECTURE LETTERS Thread Migration Prediction for Distributed Shared Caches Keun Sup Shim∗ , Mieszko Lis∗ , Omer Khan‡ , Srinivas Devadas∗ ∗ Massachusetts Institute of Technology, Cambridge, M Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2012-10-06 13:39:24 Central processing unit Microprocessors Parallel computing Threads CPU cache Multithreading Multi-core processor Microarchitecture Cache Computer hardware Computing Computer architecture
225	1 Directoryless Shared Memory Architecture using Thread Migration and Remote Access Keun Sup Shim∗ , Mieszko Lis∗ , Omer Khan‡ and Srinivas Devadas∗ ∗ Massachusetts Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2014-05-09 15:17:07 Central processing unit Microprocessors Parallel computing Instruction set architectures CPU cache X86 Multithreading Multi-core processor Microarchitecture Computer architecture Computer hardware Computing
226	Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors Ling Ren, Xiangyao Yu, Christopher W. Fletcher ∗, Marten van Dijk and Srinivas Devadas MIT CSAIL, Cambridge, MA, USA {renling, yxy, c Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-04-22 20:42:08 Central processing unit Computer architecture CPU cache Cache Oram Dynamic random-access memory B-tree Microarchitecture Computer hardware Computer memory Computing
227	To appear in Proceedings of the 28th Annual International Symposium on Computer Architecture, June 2001, Sweden. Code Layout Optimizations for Transaction Processing Workloads Alex Ramirez, Luiz Andr´e Barrosoy, Kouro Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:58 Computer architecture Cache CPU cache Computer memory Compiler optimization Inline expansion Program optimization Alpha 21164 Microarchitecture Computer hardware Computing Central processing unit
228	Appeared in the Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October[removed]Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors Parthas Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:18 Computer engineering Cache CPU cache Computer memory Microarchitecture Out-of-order execution Instruction-level parallelism Pentium Pro Parallel computing Computer architecture Computer hardware Central processing unit
229	Appeared in the Sixth International Symposium on High-Performance Computer Architecture (HPCA), January[removed]Impact of Chip-Level Integration on Performance of OLTP Workloads Luiz Andr´e Barroso, Kourosh Gharachorloo, Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:29 Computer engineering CPU cache Cache Computer memory Microprocessors PA-8000 Microarchitecture UltraSPARC III Scratchpad memory Computer hardware Computer architecture Central processing unit
230	present a free and open computer engineering seminar Line Associative Registers Architecture Matthew Sparks Abstract: Modern processor architectures suer from an ever increasing gap between processor and memory perform Add to Reading List Source URL: aggregate.ee.engr.uky.edu Language: English - Date: 2012-03-20 08:19:02 Computer engineering Computer memory Cache CPU cache Processor register Microarchitecture Computer hardware Central processing unit Computer architecture

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