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Torrellas
Results: 158

#	Item
51	Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors Marcelo Cintra, Jose´ F. Mart´ınez, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-C Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 12:21:04 Central processing unit Microprocessors CPU cache Cache Computer memory Parallel computing Microarchitecture Memory disambiguation Data structure alignment Computer hardware Computer architecture Computing
52	The Design Complexity of Program Undo Support in a General-Purpose Processor Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-10-16 18:49:08 Central processing unit Cache CPU cache Computer memory Microarchitecture AMD 10h Parallel computing LEON Speculative execution Computer hardware Computer architecture Computer engineering
53	ReViveI/O: Efficient Handling of I/O in Highly-Available Rollback-Recovery Servers∗ Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo† , and Josep Torrellas University of Illinois at Urbana-Champaign † Google {nak Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-12-16 14:06:42 Cache Disk buffer Replication Application checkpointing Device file Data buffer RAID Buffer overflow Fault-tolerant system Fault-tolerant computer systems Computing Computer hardware
54	Programming and Debugging Shared Memory Programs with Data Coloring Luis Ceze† , Christoph von Praun‡ , C˘alin Ca¸scaval‡ Pablo Montesinos# and Josep Torrellas# † Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-02-28 21:02:25 Data Computing Transactional memory Linearizability Software transactional memory Parallel computing Lock Consistency model Atomicity Transaction processing Concurrency control Data management
55	WeeFence: Toward Making Fences Free in TSO ∗ Yuelu Duan, † Abdullah Muzahid, Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-04-25 09:29:13 Computer memory Central processing unit Memory barrier CPU cache Write buffer Parallel computing Cache Compiler optimization Microarchitecture Computer architecture Computing Computer hardware
56	Prototyping Architectural Support for Program Rollback Using FPGAs Radu Teodorescu and Josep Torrellas http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-25 18:04:58 Central processing unit Application checkpointing CPU cache Debugging Debugger Rollback Computing Computer architecture Data
57	Profile-Based Energy Reduction for High-Performance Processors Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-12-10 19:52:52 Computer architecture Profilers Software optimization CPU cache Cache Computer memory Profiling Program optimization Microarchitecture Computing Computer hardware Central processing unit
58	Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization ´ Garzar´an, Lawrence Rauchwergery , and Josep Torrellas Milos Prvulovic, Mar´ıa Jesus University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-23 12:50:54 Computer memory Cache coherency Central processing unit CPU cache Cache Multi-core processor Speedup Automatic parallelization Memory hierarchy Computing Parallel computing Computer architecture
59	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, kstrauss, jtuck, torrellas}@c Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-12-21 00:54:20 Central processing unit Runahead CPU cache Microprocessors Branch predictor Memory-level parallelism Microarchitecture Instruction window Hardware scout Computer architecture Computer hardware Computer engineering
60	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection∗ Abdullah Muzahid, Norimasa Otsuki† , and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-10-23 11:07:53 Data Transaction processing Computer memory Parallel computing Linearizability CPU cache I1 Cache Q Computing Data management Concurrency control

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