Torrellas - PDFSEARCH.IO - Document Search Engine

Torrellas
Results: 158

#	Item
41	Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules ∗ Aditya Agrawal, Amin Ansari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma. Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-14 22:55:13 Computing EDRAM Memory refresh Dynamic random-access memory CPU cache Bloom filter Tile Cache Computer memory Computer hardware Visual arts
42	Scalable   Cache Miss Handling   For High MLP James Tuck, Luis Ceze, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-01-01 23:58:17 Computer engineering Computer memory Microprocessors CPU cache Cache Memory-level parallelism Runahead Intel Core Microarchitecture Computer architecture Computer hardware Central processing unit
43	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu/ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-03-10 10:28:34 Central processing unit Instruction set
44	Rebound: Scalable Checkpointing for Coherent Shared Memory Rishi Agarwal, Pranav Garg, and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,garg11,torrella}@illinois.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-04-01 11:24:25 Central processing unit Microprocessors Application checkpointing Computer memory Parallel computing CPU cache Multi-core processor AMD 10h Microarchitecture Computer architecture Computer hardware Computing
45	WeeFence: Toward Making Fences Free in TSO Yuelu Duan, Abdullah Muzahid, Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-07-04 19:09:55 Wing fence Fence Structure
46	Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-04-04 17:00:54 Computing Microprocessors Threads Parallel computing CPU cache Computer memory Multithreading Microarchitecture Threading Computer hardware Computer architecture Central processing unit
47	Dynamically Detecting and Tolerating IF-Condition Data Races Shanxiang Qi (Google), Abdullah Muzahid (University of San Antonio), Wonsun Ahn, Josep Torrellas University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-02-20 12:55:50 Concurrent computing Concurrency control Anti-patterns Concurrency Race condition Lock Futures and promises Parallel computing Debugging Computing Software bugs Computer programming
48	Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors Marcelo Cintra Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-12-10 19:25:05 Computer architecture CPU cache Memory disambiguation Squash Branch predictor Parallel computing Central processing unit Monitor Speculative execution Computer memory Computing Computer hardware
49	Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates Brian Greskamp Smruti R. Sarangi Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-02-17 12:35:11 Failure Survival analysis Electronic engineering Heat transfer Systems engineering Thermal runaway Reliability engineering Mean time between failures Battery Engineering Electrical engineering Technology
50	Variation Aware Application Scheduling and Power Management for Chip Multiprocessors Radu Teodorescu* and Josep Torrellas Computer Science Department University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-29 12:04:40 Opteron IEC 60320 Dictionary of chemical formulas/Merge

UPDATE