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Torrellas
Results: 158

#	Item
131	Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically ∗ Abdullah Muzahid† , Shanxiang Qi, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstra Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2012-11-04 16:19:00 Computing Central processing unit Computer architecture CPU cache Cache Parallel computing MSI protocol False sharing Cache coherency Computer memory Computer hardware
132	Efficient and Flexible Architectural Support for Dynamic Monitoring Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu and Josep Torrellas Department of Computer Science, University of Illinois at Urbana-Champaign {yyzhou,pinzho Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-12-21 01:01:36 Computer programming CPU cache C dynamic memory allocation Debugging C Profiling Pointer Memory leak Buffer overflow Computing Software bugs Software engineering
133	BlueShift: Designing Processors for Timing Speculation from the Ground Up∗ Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, and Craig Zilles Departments of Computer Science and o Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-01-11 13:30:20 Electronic engineering Microprocessors Parallel computing Microarchitecture Intel Core Branch predictor Physical design CPU cache Static timing analysis Computer hardware Computer architecture Central processing unit
134	Rapid Prototyping in Architecture Research using Hardware Hooks in COTS Systems Smruti R. Sarangi, Brian Greskamp and Josep Torrellas Department of Computer Science, University of Illinois http://iacoma.cs.uiuc.edu Abstr Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-06-25 20:28:19 Central processing unit Computer memory Northbridge Hardware performance counter P5 Hyper-threading Intel Microarchitecture Memory address Computer hardware Computer architecture Computing
135	Are We Ready for High Memory-Level Parallelism? Luis Ceze, James Tuck and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign Email: {luisceze,jtuck,torrella}@cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-02-06 00:34:38 Central processing unit Computer memory Cache CPU cache Runahead Microprocessors Memory-level parallelism Microarchitecture AMD 10h Computer architecture Computer hardware Computer engineering
136	Submitted to the Workshop on the Evaluation of Software Defect Detection Tools Deploying Architectural Support for Software Defect Detection in Future Processors Yuanyuan Zhou and Josep Torrellas Department of Computer Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-10-16 19:01:21 ECC memory Computer architecture Embedded systems Software engineering Electronics Debuggers Debugging Computing Software
137	PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection∗ Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou and Josep Torrellas Department of Computer Science, University of Illinois at Urb Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:17:37 Software bug Code coverage Software quality Benchmark Program analysis Software engineering Software testing Software metrics
138	Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules Aditya Agrawal, Amin Ansari and Josep Torrellas http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-02-19 00:21:07 Josep Torrellas Capacitor Torrellas Computing Technology Computer memory EDRAM Dynamic random-access memory
139	Vt Variation Effects on Lifetime Reliability Brian Greskamp Smruti R. Sarangi Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-24 11:30:50 Systems engineering Systems science Electronic design automation Design for X Mean time between failures Electromigration Failure Survival analysis Reliability engineering
140	DeLorean: Recording and Deterministically Replaying Shared Memory Multiprocessor Execution Efficiently Pablo Montesinos, Luis Ceze* and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Cham Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 18:23:34 Delorean Thread

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