CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging∗ Smruti R. Sarangi, Brian Greskamp, and Josep Torrellas Department of Computer Science, University of Illinois http://iacoma.cs.uiuc.edu Abstract

Source URL: iacoma.cs.uiuc.edu

• Motherboard
• Computer memory
• Clock signal
• Digital electronics
• Conventional PCI
• Interrupt
• Front-side bus
• CAS latency
• Bus
• Computer hardware
• Electronic engineering
• Computer buses

Energy-Efficient Hybrid Wakeup Logic Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT

Source URL: iacoma.cs.uiuc.edu

• Parallel computing
• Classes of computers
• Central processing unit
• Superscalar
• Branch predictor
• Reduced instruction set computing
• Instruction set
• Very long instruction word
• Microarchitecture
• Computer architecture
• Computing
• Computer hardware

Microsoft PowerPoint - 32-torrellas-presentation

Source URL: iacoma.cs.uiuc.edu

Capo: A Software-Hardware Interface for Practical Deterministic Multiprocessor Replay Pablo Montesinos, Matthew Hicks, Samuel T. King and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Ch

Source URL: iacoma.cs.uiuc.edu

• Replay system
• Software
• Computer architecture
• Threads
• Computing
• Concurrent computing
• REPLAY

BulkCompactor: Optimized Deterministic Execution via Conflict-Aware Commit of Atomic Blocks∗ Yuelu Duan, Xing Zhou, Wonsun Ahn, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu A

Source URL: iacoma.cs.uiuc.edu

• Chunk
• C dynamic memory allocation
• Computing

DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently∗ Pablo Montesinos, Luis Ceze† and Josep Torrellas Department of Computer Science University of Illinois at Urbana

Source URL: iacoma.cs.uiuc.edu

• Central processing unit
• Chunk
• CPU cache
• Parallel computing
• C dynamic memory allocation
• Computer memory
• Computing
• Computer hardware

Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors

Source URL: iacoma.cs.uiuc.edu

• Speculative multithreading
• Josep Torrellas
• Speedup
• Central processing unit
• POWER5
• Computing
• Parallel computing
• Standard Performance Evaluation Corporation

Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies Aditya Agrawal, Prabhat Jain, Amin Ansari and Josep Torrellas University of Illinois at Urbana Champaign http://iacoma.cs.uiuc.ed

Source URL: iacoma.cs.uiuc.edu

• CPU cache
• Dynamic random-access memory
• Refresh rate
• Cache
• Three-phase
• Computer memory
• Computer hardware
• Computing

VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects ∗ Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas University of Illinois at Urb

Source URL: iacoma.cs.uiuc.edu

• Regression analysis
• Computer memory
• MOSFET
• Normal distribution
• Dynamic random-access memory
• Standard deviation
• Threshold voltage
• Systematic error
• Errors and residuals in statistics
• Statistics
• Data analysis
• Measurement

Microsoft PowerPoint - present_pact03 [Compatibility Mode]

Source URL: iacoma.cs.uiuc.edu

• Champaign–Urbana metropolitan area
• Torrellas
• Champaign
• Urbana
• Illinois
• Illinois Terminal
• Geography of Illinois
• Champaign County
• Illinois
• Illinois