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Systolic array
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1	1160 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 12, NO. 12, DECEMBER 2002 Transactions Letters________________________________________________________________ Efficient and Configurable Full-Se Add to Reading List Source URL: www.inesc-id.pt Language: English - Date: 2005-11-28 09:11:59 Parallel computing Video compression Block-matching algorithm Inter frame Field-programmable gate array Systolic array VHDL Cell Motion compensation Asynchronous array of simple processors
2	Polyhedral Model: Past Present & Future title shamelessly copied from Feautrier’s LCPC 2009 keynote Sanjay Rajopadhye Add to Reading List Source URL: labexcompilation.ens-lyon.fr Language: English - Date: 2013-05-14 05:22:23 Linear algebra Compiler optimizations Parallel computing Projective geometry Euclidean geometry Vector space Automatic parallelization Systolic array Recurrence relation Algebra Mathematics Geometry
3	SDPS Journal http://hartenstein.de/SDPS/SDPSjournal.html Transactions of the SDPS: Integrated Design & Process Science Add to Reading List Source URL: hartenstein.de Language: English - Date: 2007-10-05 01:53:45 Parallel computing Electronics Computer architecture High-performance reconfigurable computing Systolic array Data stream Programming paradigm Multi-core processor John von Neumann Computing Reconfigurable computing Electronic engineering
4	An FPGA architecture for DRAM-based systolic computations Norman Margolus Boston University Center for Computational Science and MIT Artificial Intelligence Laboratory Abstract Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2005-01-16 13:05:57 Computer architecture Central processing unit Dynamic random-access memory Digital electronics Field-programmable gate array Cell Parallel computing Microprocessor CPU cache Computer hardware Computer memory Electronic engineering
5	Karl Steinbuch about how to invent something Reiner Hartenstein, TU-Kaiserslautern and ITIV If you invent something, you may suffer from the Tunnel Vision Syndrome. Karl Steinbuch’s point of view (fig. 3) has been illu Add to Reading List Source URL: www.fpl.uni-kl.de Language: English - Date: 2014-12-21 10:22:22 Electronics Computer architecture Systolic array Classes of computers Field-programmable gate array Data stream Von Neumann architecture John von Neumann Computer Computing Electronic engineering Reconfigurable computing
6	RETROSPECTIVE: A Data Locality Optimizing Algorithm Monica S. Lam Computer Systems Laboratory Stanford University Add to Reading List Source URL: suif.stanford.edu Language: English - Date: 2003-01-05 22:10:50 Loop optimization Parallel computing Automatic parallelization Vectorization Systolic array Algorithm Frameworks supporting the polyhedral model Scalable parallelism Compiler optimizations Computing Software engineering
7	-18 March 13, 2002 A Systolic Array for Implementing LRU Replacement J.P. Grossman Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2002-08-16 14:57:27 Cache algorithms CPU cache Array Systolic array Pseudo-LRU Cache Computing Computer hardware
8	NOVEL GRAPH PROCESSOR ARCHITECTURE Novel Graph Processor Architecture William S. Song, Jeremy Kepner, Vitaliy Gleyzer, Huy T. Nguyen, and Joshua I. Kramer Add to Reading List Source URL: www.ll.mit.edu Language: English - Date: 2013-10-17 13:27:38 Sparse matrix Array Cell Systolic array Throughput Distributed memory Parallel computing Computing Multi-core processor
9	1 Why we need Reconfigurable Computing Education Reiner Hartenstein, IEEE life fellow, TU Kaiserslautern, http://hartenstein.de Abstract. Reconfigurable Computing, the second RAM-based Add to Reading List Source URL: xputers.informatik.uni-kl.de Language: English - Date: 2006-03-30 12:23:15 Electronics Reconfigurable datapath array Systolic array Field-programmable gate array High-performance reconfigurable computing Parallel computing Xilinx CPU design Programmable logic device Reconfigurable computing Electronic engineering Computing
10	R.W. Hartenstein, A.G. Hirschbiel, M. Riedmuller, K. Schmidt, M.Weber: A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24, Hawaii Int. Conference on System Sciences, Koloa Hawaii, 1991 A Add to Reading List Source URL: hartenstein.de Language: English - Date: 2012-03-09 12:37:00 Computer hardware Parallel computing Cache Systolic array Instruction set Microcode Computer Computer architecture Central processing unit Computing