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Von Neumann architecture
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1	Advanced Parallel Architecture Lesson 3 Annalisa Massini Von Neumann Architecture Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-03-03 11:00:54 Computing Central processing unit Computer engineering Computer hardware Computer architecture Classes of computers Vacuum tube computers Accumulator Processor register Computer Von Neumann architecture Instruction set
2	Implementing the Quantum von Neumann Architecture with Superconducting Circuits Matteo Mariantoni1,4,§ , H. Wang1,∗ , T. Yamamoto1,2 , M. Neeley1,† , Radoslaw C. Bialczak1 , Y. Chen1 , M. Lenander1 , Erik Lucero1 , Add to Reading List Source URL: www.ee.ucr.edu Language: English - Date: 2012-05-09 17:52:14
3	Succinct Non-Interactive Zero Knowledge for a von Neumann Architecture Add to Reading List Source URL: www.usenix.org Language: English Complexity classes Circuit complexity Computational complexity theory Zero-knowledge proof Non-interactive zero-knowledge proof SM-62 Snark XTR NC NP Proof of knowledge Computer ZK
4	UCRL-TREarly Computing and Its Impact on Lawrence Livermore National Laboratory Add to Reading List Source URL: e-reports-ext.llnl.gov Language: English - Date: 2007-04-16 19:30:05 University of Pennsylvania Turing machine Alan Turing ENIAC John Mauchly Von Neumann architecture John von Neumann J. Presper Eckert Universal Turing machine Computing Classes of computers History of computing hardware
5	POSTER: Succinct Non-Interactive Zero Knowledge for a von Neumann Architecture Eli Ben-Sasson∗ , Alessandro Chiesa† , Eran Tromer‡ , Madars Virza† ∗ Technion, Add to Reading List Source URL: www.ieee-security.org - Date: 2014-05-07 16:20:45
6	Machines, langages et langages machines Gilles Dowek I. De quoi est compose´ un ordinateur L’architecture de Von Neumann Add to Reading List Source URL: who.rocq.inria.fr - Date: 2015-05-21 03:36:51
7	Summary Report from 2015 Neuro-Inspired Computational Elements (NICE) Workshop Information Processing and Computation Systems beyond von Neumann/Turing Architecture and Moore’s Law Limits 2015 Add to Reading List Source URL: science.energy.gov Language: English - Date: 2015-04-03 07:56:05 Science Electrical engineering Neuromorphic engineering Computing Artificial neural network Computational science Exascale computing Cellular neural network Computational neuroscience Neuroscience Neural networks
8	SDPS Journal http://hartenstein.de/SDPS/SDPSjournal.html Transactions of the SDPS: Integrated Design & Process Science Add to Reading List Source URL: hartenstein.de Language: English - Date: 2007-10-05 01:53:45 Parallel computing Electronics Computer architecture High-performance reconfigurable computing Systolic array Data stream Programming paradigm Multi-core processor John von Neumann Computing Reconfigurable computing Electronic engineering
9	Karl Steinbuch about how to invent something Reiner Hartenstein, TU-Kaiserslautern and ITIV If you invent something, you may suffer from the Tunnel Vision Syndrome. Karl Steinbuch’s point of view (fig. 3) has been illu Add to Reading List Source URL: www.fpl.uni-kl.de Language: English - Date: 2014-12-21 10:22:22 Electronics Computer architecture Systolic array Classes of computers Field-programmable gate array Data stream Von Neumann architecture John von Neumann Computer Computing Electronic engineering Reconfigurable computing