An Operational Semantics of Cache Coherent Multicore Architectures∗ Shiji Bijo, Einar Broch Johnsen, Ka I Pun, and S. Lizeth Tapia Tarifa University of Oslo, Norway {shijib, einarj, violet, sltarifa}@ifi.uio.no

Source URL: einarj.at.ifi.uio.no

• Cache coherency
• Parallel computing
• Computer architecture
• Computer memory
• computing
• CPU cache
• MSI protocol
• Coherent cache
• Cache
• MESI protocol
• Multi-core processor
• Draft:Cache memory

C HA PT E R 1 9 The Form Processor OVERVIEW Our form processing application allows a site administrator to process the results of Web-based forms in a number of ways. The script can be used to generate dynamic E-mail or

Source URL: www.extropia.com

• World Wide Web
• HTML
• Scripting languages
• Cross-platform software
• Form
• Common Gateway Interface
• JavaScript
• HTML element
• Environment variable
• Server
• Email
• Semantic URL attack

VIMICRO VC0363 USB 2.0 Camera Processor VC0363 is a low cost USB 2.0 camera processor targeting for embedded Notebook webcam and

Source URL: www.vimicro.com.cn

• Microcontrollers
• IC
• USB
• Webcam

VIMICRO VC0338 USB 2.0 Camera Processor VC0338 is a high performance USB 2.0 camera processor targeting for high quality standard-alone

Source URL: www.vimicro.com.cn

• Microcontrollers
• Linux-based devices
• ARM architecture
• Single-board computers
• USB
• C8051
• Banana Pi

DEGAS: Dynamic Global Address Space programming environments Katherine Yelick, Principal Investigator1 Lawrence Berkeley National Laboratory, Berkeley, California Vivek Sarkar, Co-Principal Investigator2 Rice University,

Source URL: crd.lbl.gov

• Parallel computing
• Partitioned global address space
• Coarray Fortran
• Unified Parallel C
• X10
• Parallel programming model
• Multi-core processor
• PGAS
• Matrix multiplication algorithm
• Fortran
• Distributed computing
• OpenMP

High Resolution Digital Pulse Processor MADE IN JAPAN APV81041GSPS), APV8508500MSPS)

Source URL: www.techno-ap.com

H-Store: A Specialized Architecture for High-throughput OLTP Applications Evan Jones (MIT) Andrew Pavlo (Brown) 13th Intl. Workshop on High Performance Transaction Systems

Source URL: hpts.ws

• Data management
• Databases
• Online transaction processing
• Transaction processing
• Microprocessors
• Nehalem
• Xeon
• Multi-core processor

AR15 - RECORD COLLECTION – UNBILLED RECEIPT (UNCLEARED COLLECTIONS) Source Document:

Source URL: www.dof.ca.gov

• Payment systems
• Point of sale
• Bank
• Accounts receivable
• Deposit slip
• Payment processor
• Payment
• Invoice
• Cheque

A preliminary evaluation of the hardware acceleration of the Cray Gemini Interconnect for PGAS languages and comparison with MPI Hongzhang Shan, Nicholas J. Wright, John Shalf and Katherine Yelick CRD and NERSC

Source URL: crd.lbl.gov

• Parallel computing
• Message Passing Interface
• Partitioned global address space
• MPICH
• Coarray Fortran
• Cray
• Multi-core processor
• Blue Gene
• MVAPICH
• MPI
• K computer
• Parallel Virtual Machine

CS:APP2e Web Aside ARCH:VLOG Verilog Implementation of a Pipelined Y86 Processor∗ Randal E. Bryant David R. O’Hallaron June 5, 2012

Source URL: csapp.cs.cmu.edu

• Hardware description languages
• Electronic design automation
• Verilog
• Digital electronics
• Field-programmable gate array
• High-level synthesis
• Verilog-AMS
• SystemVerilog