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Pipelining
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81	The Energy Impact of Aggressive Loop Fusion YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, and David H. Albonesi Departments of Electrical and Computer Engineering and of Computer Science University of Roc Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2003-12-11 10:02:03 Computer architecture Central processing unit Cache CPU cache Computer memory Parallel computing Loop optimization Software pipelining Branch predictor Computing Compiler optimizations Software engineering
82	On-the-Fly Pipeline Parallelism I-Ting Angelina Lee* Charles E. Leiserson* * MIT Add to Reading List Source URL: supertech.csail.mit.edu Language: English - Date: 2014-09-16 08:27:51 Compiler optimizations Cilk Parallel computing Application programming interfaces Software pipelining OpenMP Sequence container Pipeline Instruction pipeline Computing Computer programming Software engineering
83	Looking for Some Good People Unique Rewards! The Canadian pipeline industry is looking for some good people who are attracted to the flexibility and focused work that a pipelining Add to Reading List Source URL: www.pipeline.ca Language: English - Date: 2010-05-12 21:38:27 Water Construction Shipping Construction of the Trans-Alaska Pipeline System Piping Pipeline transport Pipe
84	Design and Evaluation of a Compiler Algorithm for Prefetching Todd C. Mowry, Monica S. Lam and Anoop Gupta Computer Systems Laboratory Stanford University, CA 94305 Add to Reading List Source URL: suif.stanford.edu Language: English - Date: 2006-06-25 21:11:32 Computer hardware Computer programming CPU cache Loop nest optimization Cache Memory hierarchy Software pipelining Lookup table Acumem SlowSpotter Computing Computer memory Compiler optimizations
85	RETROSPECTIVE: Software Pipelining: An Effective Scheduling Technique for VLIW Machines Monica S. Lam Computer Systems Laboratory Add to Reading List Source URL: suif.stanford.edu Language: English - Date: 2003-01-05 22:11:04 Computer engineering Software pipelining Very long instruction word Explicitly parallel instruction computing Instruction scheduling Instruction-level parallelism Central processing unit Multiflow Futures and promises Computing Computer architecture Compiler optimizations
86	Software Pipelining: An Effective Scheduling Technique for VLIW Machines Monica Lam of Computer Science Carnegie Mellon University Add to Reading List Source URL: suif.stanford.edu Language: English - Date: 2004-01-27 05:02:35 Software engineering Software pipelining Very long instruction word Loop unwinding Parallel computing Control flow Trace scheduling Program optimization For loop Compiler optimizations Computing Concurrent computing
87	MIPS Assembly Language Guide MIPS is an example of a Reduced Instruction Set Computer (RISC) which was designed for easy instruction pipelining. MIPS has a “Load/Store” architecture since all instructions (other than Add to Reading List Source URL: www.cs.uni.edu Language: English - Date: 2008-03-04 08:20:27 Instruction set architectures MIPS architecture Calling convention SPIM Processor register 64-bit Subroutine Computer architecture Computing Computer programming
88	Exploiting Vector Parallelism in Software Pipelined Loops Samuel Larsen, Rodric Rabbah and Saman Amarasinghe MIT Computer Science and Artificial Intelligence Laboratory {slarsen,rabbah,saman}@mit.edu Abstract Add to Reading List Source URL: groups.csail.mit.edu Language: English - Date: 2009-01-29 13:06:12 Computer programming Vectorization Loop optimization Instruction scheduling Software pipelining AltiVec SIMD Central processing unit Loop dependence analysis Computing Compiler optimizations Software engineering
89	INTRODUCTION These notes, used in a two-part four-hour short course, introduce the reader (mostly the scientific programmer) to some of the main scalar optimization concepts and techniques associated with modern supersca Add to Reading List Source URL: sc.tamu.edu Language: English - Date: 2006-07-28 17:21:05 Central processing unit R10000 CPU cache Superscalar Software pipelining Instruction set R8000 MIPS architecture Computer hardware Computer architecture Computing
90	--06 April 20, 2000 Cheap Out-of-Order Execution using Delayed Issue J.P. Grossman Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2001-05-16 17:41:22 Parallel computing Central processing unit Classes of computers Register renaming Superscalar Very long instruction word Software pipelining Tomasulo algorithm Instruction set Computer architecture Computing Computer engineering

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