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Microprocessors
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#	Item
321	AMD “Kabini” APU SOC DAN BOUVIER BEN BATES, WALTER FRY, SREEKANTH GODEY HOT CHIPS 25 AUGUST 2013 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-08-16 18:10:18 Central processing unit Microprocessors Bobcat Microcode Multi-core processor CPU cache Computer hardware Computer architecture Computing
322	Level-3 BLAS on Myriad Multi-Core Media-Processor SoC 1 Tomasz Szydzik 1 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2014-08-04 15:33:27 Numerical linear algebra Numerical software Computer memory Embedded microprocessors Central processing unit General Matrix Multiply LEON Direct memory access CPU cache Computer hardware Computer architecture Computing
323	• Silicon Graphics TFP Micro-Supercomputer Chipset I Iｾ Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:45:50 Microprocessors R4000 MIPS architecture CPU cache Superscalar R8000 Alpha 21064 Computer hardware Computer architecture Computing
324	Pursuant to 17 CFR 240.24b-2, confidential information has been omitted in places marked “[*]” and has been filed separately with the Securities and Exchange Commission pursuant to a Confidential Treatment Applicat Add to Reading List Source URL: download.intel.com Language: English - Date: 2011-01-10 15:15:05** Microprocessors Instruction set architectures Fabless semiconductor companies Intel Nvidia XScale Multi-core processor Itanium Celeron Computer hardware Computer architecture Computing
325	Towards Nanocomputer Architecture Paul Beckett, Andrew Jennings School of Electrical & Computer Systems Engineering RMIT University PO Box 2476V Melbourne, Australia [removed], [removed] Add to Reading List Source URL: www.cellmatrix.com Language: English - Date: 2002-04-14 21:49:59 Computer architecture Parallel computing Microprocessors Digital electronics Classes of computers Reconfigurable computing Field-programmable gate array Stream processing Logic gate Computing Electronic engineering Electronics
326	OpenSPARC – An Open Platform for Hardware Reliability Experimentation Ishwar Parulkar and Alan Wood Sun Microsystems, Inc. James C. Hoe and Babak Falsafi Carnegie Mellon University Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 23:46:10 Microprocessors Parallel computing Central processing unit Threads OpenSPARC UltraSPARC T2 Multi-core processor Multithreading SPARC Computer hardware Computer architecture Electronic engineering
327	REDW1992 Revision 0.1, Dec[removed]Prepared by: David M. Hiemstra Add to Reading List Source URL: www.nsrec.com Language: English - Date: 2005-12-14 11:19:39 Microprocessors National Semiconductor Application-specific integrated circuit R3000 Electronic engineering Electronics Computer hardware
328	Alpha Microprocessors Motherboard Debug Monitor User’s Guide Order Number: EC–QHUVG–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:10 Computer buses IBM PC compatibles Instruction set architectures DEC Alpha Conventional PCI PCI configuration space Debug Motherboard Alpha 21164 Computing Computer hardware Computer architecture
329	Facelift: Hiding and Slowing Down Aging in Multicores∗ Abhishek Tiwari and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-09-13 00:18:06 Computer hardware Computer architecture Integrated circuits Microprocessors Electronic design Frequency scaling Microarchitecture Hot carrier injection CPU cache Electronic engineering Electronics Central processing unit
330	Scalable   Cache Miss Handling   For High MLP James Tuck, Luis Ceze, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-01-01 23:58:17 Computer engineering Computer memory Microprocessors CPU cache Cache Memory-level parallelism Runahead Intel Core Microarchitecture Computer architecture Computer hardware Central processing unit

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