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Microprocessors
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#	Item
21	eSi-1600 – 16-bit, low-cost & low-power CPU EnSilica’s eSi-1600 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. It offers similar performance t Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-10-14 01:56:25 Computing Computer architecture Computer engineering Embedded microprocessors Instruction set architectures EnSilica ESi-RISC Central processing unit JTAG ARC 16-bit Reduced instruction set computing
22	The Linux Scheduler: a Decade of Wasted Cores Jean-Pierre Lozi Baptiste Lepers Justin Funston Add to Reading List Source URL: www.ece.ubc.ca Language: English - Date: 2016-04-17 18:23:58 Computing Concurrent computing Computer architecture Parallel computing Scheduling Microprocessors Planning Work stealing Multithreading Completely Fair Scheduler Thread Load
23	5e Rencontres Arithmétique de l’Informatique Mathématique (RAIMDijon, 20-22 juin 2012 Synthesis of fixed-point programs based on instruction selection ... the case of polynomial evaluation Add to Reading List Source URL: raim2012.u-bourgogne.fr Language: English - Date: 2012-07-16 09:26:12 Computing Computer architecture Central processing unit Computer hardware Computer arithmetic Microprocessors Floating point Floating-point unit Fixed-point arithmetic Embedded system
24	HPCToolkit User’s Manual John Mellor-Crummey Laksono Adhianto, Mike Fagan, Mark Krentel, Nathan Tallent Rice University For HPCToolkitRevision) December 15, 2015 Add to Reading List Source URL: hpctoolkit.org Language: English - Date: 2016-07-29 19:18:42 Computing Computer programming Software engineering Parallel computing Software optimization Microprocessors System administration Application programming interfaces Profiling Multi-core processor Instrumentation Thread
25	MG_Boilerplate10-WP3b arial Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-07-31 22:34:01 Computing Computer architecture Computer engineering Computer memory Central processing unit Instruction set architectures Embedded microprocessors Random-access memory Cell ARC CPU cache Processor register
26	eSi-3250 – 32-bit, high-performance CPU EnSilica’s eSi-3250 CPU IP core is a high-performance processor ideal for integration into ASIC and/or FPGA designs with off-chip memories. The eSi-3250 is suited to a wide ran Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-10-14 01:56:26 Computer architecture Computing Computer engineering Instruction set architectures Embedded microprocessors ESi-RISC EnSilica Soft microprocessor Nios II
27	Power and Energy Code Profiling in Pharo Alexandre Bergel Pleiad Lab, DCC, University of Chile Abstract Add to Reading List Source URL: dl.dropboxusercontent.com Language: English Computing Computer hardware Computer architecture Central processing unit Electric power Microprocessors Computer performance Clock signal Benchmark Standard Performance Evaluation Corporation CPU power dissipation CPU cache
28	MG_Boilerplate10-WP3b arial Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-07-31 22:34:01 Computer architecture Computing Computer engineering Computer memory System on a chip Embedded microprocessors Instruction set architectures Application-specific integrated circuit Random-access memory CPU cache ARC Cell
29	WiMOD iM880B Datasheet Document ID: IMST GmbH Add to Reading List Source URL: www.wireless-solutions.de Language: English - Date: 2016-03-11 09:10:57 Computing Electronics Wireless sensor network Data transmission Microcontrollers ARM architecture Embedded microprocessors DBm STM32 Radio frequency Modulation Sensor node
30	Managing Power Consumption in Networks on Chips Tajana Simunic Stephen Boyd HP Labs & Stanford University Add to Reading List Source URL: seelab.ucsd.edu Language: English - Date: 2012-06-04 16:50:18 Computer hardware Electromagnetism Electronics Energy conservation Microprocessors Electronic design automation Electric power Computers and the environment Power management Network on a chip Open Core Protocol Intel Core

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