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Microarchitecture
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#	Item
201	The Impact of Communication Style on Machine Resource Usage for the iWarp Parallel Processor T. Gross, A. Hasegawa, S. Hinrichs, D. O’Hallaron, and T. Stricker November, 1992 CMU-CS[removed] Add to Reading List Source URL: www.cs.inf.ethz.ch Language: English - Date: 1997-01-16 13:50:32 Central processing unit Computer architecture IWarp WARP Microprocessors Instruction set CPU cache Process Microarchitecture Computing Parallel computing Supercomputers
202	ECE3056 - Architecture, Concurrency, and Energy in Computation[removed]Prerequisites: ECE 2031/20X2 [min C] and ECE[removed]min C] Corequisites: None Catalog Description: Basic organizational principles of the major c Add to Reading List Source URL: pe.gatech.edu Language: English - Date: 2014-12-19 12:26:28 Computer engineering Microprocessors Computer memory Firmware Microcode Hardware description language Microarchitecture Parallel computing Memory hierarchy Computer architecture Computer hardware Central processing unit
203	Performance Nonmonotonicities: A Case Study of the UltraSPARC Processor by Nathaniel A. Kushman Submitted to the Department of Electrical Engineering and Computer Science Add to Reading List Source URL: supertech.csail.mit.edu Language: English - Date: 2014-09-16 08:27:50 Microprocessors UltraSPARC Central processing unit Microarchitecture SPARC Superscalar Computer Sun Ultra series UltraSPARC T1 Computer hardware Computer architecture Electronic engineering
204	Portable High-Performance Programs by Matteo Frigo Laurea, Universit`a di Padova[removed]Dottorato di Ricerca, Universit`a di Padova (1996) Add to Reading List Source URL: supertech.csail.mit.edu Language: English - Date: 2014-09-16 08:27:49 Cilk Charles E. Leiserson Computer architecture Microprocessors Digital signal processing Cache-oblivious algorithm Parallel computing Thread Microarchitecture Computing Cache Central processing unit
205	Hardware Assistance for Trustworthy Systems through 3-D Integration Jonathan Valamehr† , Mohit Tiwari‡ , and Timothy Sherwood‡ † Department of Electrical and Computer Engineering Add to Reading List Source URL: www.cisr.us Language: English - Date: 2010-11-15 16:22:59 Microprocessors Central processing unit Computer memory Cache CPU cache Multi-core processor Parallel computing Microarchitecture Dynamic random-access memory Computer hardware Computing Computer architecture
206	PRODUCT BRIEF Intel® Microarchitecture (Codename Haswell) and 4th Generation Intel® Core™ Processors New Microarchitecture for 4th Gen Intel® Core™ Processor Platforms Add to Reading List Source URL: www.intel.la Language: English - Date: 2014-03-01 02:27:52 Computing Out-of-band management Intel vPro Intel Nvidia Ion Hyper-threading X86 virtualization Celeron Centrino System software Computer hardware X86 architecture
207	Processor Architecture, Nios II Processor Reference Handbook Add to Reading List Source URL: www.altera.com Language: English - Date: 2014-02-14 18:17:39 Central processing unit Nios II Joint Test Action Group Instruction set Nios embedded processor Microarchitecture Computer architecture Computer hardware Computer engineering
208	Appears in the Proceedings of the 27 Annual International Symposium on Computer Architecture Add to Reading List Source URL: www.cs.utexas.edu Language: English - Date: 2001-08-26 17:50:45 Central processing unit Computer memory Clock signal Microarchitecture Microprocessors CPU cache FO4 Dynamic random-access memory Intel 80486 Computer hardware Computer architecture Electronic engineering
209	TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. XX, NO. YY, ZZZ[removed]Performance Models for Network Processor Design Tilman Wolf, Member, IEEE, Mark A. Franklin, Fellow, IEEE Add to Reading List Source URL: www.ecs.umass.edu Language: English - Date: 2013-12-04 11:29:39 Central processing unit Microprocessors Parallel computing Threads CPU cache Multi-core processor Microarchitecture Cell Multithreading Computer hardware Computer architecture Computing
210	A Coarse Grained Reconfigurable Architecture Framework supporting Macro-Dataflow Execution Add to Reading List Source URL: etd.ncsi.iisc.ernet.in Language: English - Date: 2014-04-23 02:19:41 Parallel computing Dataflow Instruction-level parallelism Multi-core processor Microarchitecture Compiler Central processing unit Granularity Computer architecture Computing Computer engineering

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