Jason Cong - PDFSEARCH.IO - Document Search Engine

Jason Cong
Results: 11

#	Item
1	FPGA’2013 Panel Are FPGAs Suffering from the Innovator’s Dilemma? Moderator: Jason Cong, UCLA Panelists Add to Reading List Source URL: cadlab.cs.ucla.edu - Date: 2013-02-19 20:09:58
2	An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 00:13:15 Integrated circuits Electronic design Placement Logic synthesis Field-programmable gate array Jason Cong Complex programmable logic device Application-specific integrated circuit Electronic engineering Electronics Electronic design automation
3	A Scalable, High-Performance Customized Priority Queue Muhuan Huang,* Kevin Lim+ and Jason Cong* * University of California, Los Angeles Computer Science Department Add to Reading List Source URL: vast.cs.ucla.edu Language: English - Date: 2014-09-03 16:10:32 Priority queue Computer science Queue Binary heap Heap Scheduling D-ary heap Double-ended queue Self-balancing binary search tree Abstract data types Graph theory Computing
4	Accelerating Monte Carlo based SSTA Using FPGA Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan and Yi Zou Computer Science Department, University of California, Los Angeles Los Angeles, CA 9009 Add to Reading List Source URL: cadlab.cs.ucla.edu Language: English - Date: 2010-02-11 21:54:56 Formal methods Electronic design automation Field-programmable gate array Statistical static timing analysis Static timing analysis Standard cell Application-specific integrated circuit Integrated circuit design Pattern matching Electronic engineering Electronics Integrated circuits
5	Microsoft Word - resume10.doc Add to Reading List Source URL: cadlab.cs.ucla.edu Language: English - Date: 2010-03-01 17:23:10 Fabless semiconductor companies Field-programmable gate array Jason Cong Logic synthesis Altera Application-specific integrated circuit Special Interest Group on Design Automation Computing with Memory Synplicity Electronic engineering Electronics Digital electronics
6	230 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Optimality Study of Logic Synthesis for LUT-Based FPGAs Add to Reading List Source URL: cadlab.cs.ucla.edu Language: English - Date: 2007-01-18 13:56:58 Digital electronics Electronic design Integrated circuits Field-programmable gate array Logic synthesis Xilinx Logic optimization Jason Cong Algorithm Electronic engineering Electronics Electronic design automation
7	Some Professional Highlights: 2009-‐present Steven Nowick ([removed]) Below is a list of some highlight in the last 5 years, includi Add to Reading List Source URL: www.cs.columbia.edu Language: English - Date: 2014-08-10 17:10:46 Jason Cong Year of birth missing Academia Association for Computing Machinery
8	A Fully Pipelined and Dynamically Composable Architecture of CGRA Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao and Peipei Zhou Computer Science Department University of California, Los Angeles Los Angeles, California, Add to Reading List Source URL: vast.cs.ucla.edu Language: English - Date: 2014-04-13 17:33:49 Computer memory Models of computation Parallel computing Reconfigurable computing Field-programmable gate array CPU cache Direct memory access Kahn process networks Computer cluster Computing Electronic engineering Computer hardware
9	Cell: ([removed]E-mail: [removed] Homepage: http://cadlab.cs.ucla.edu/~kirill/ Current Address: 5400 Lindley Ave #103 Encino, CA 91316 Add to Reading List Source URL: cadlab.cs.ucla.edu Language: English - Date: 2010-03-01 17:22:48 Fabless semiconductor companies Field-programmable gate array Jason Cong Logic synthesis Altera Application-specific integrated circuit Special Interest Group on Design Automation Computing with Memory Synplicity Electronic engineering Electronics Digital electronics
10	Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs Jason Cong and Kirill Minkovich Computer Science Department University of California, Los Angeles Los Angeles, CA 90095, USA Add to Reading List Source URL: cadlab.cs.ucla.edu Language: English - Date: 2007-02-13 15:10:27 Mathematical logic Implicant Lookup table Canonical form Boolean satisfiability problem Conjunctive normal form Binary decision diagram Truth table Boolean function Boolean algebra Theoretical computer science Mathematics

UPDATE