<--- Back to Details
First PageDocument Content
POWER6 / Chipkill / CPU cache / IBM POWER / POWER5 / Dynamic random-access memory / Multi-core processor / RAM parity / IBM z10 / Computer memory / Computer hardware / Computing
Date: 2013-07-27 23:58:01
POWER6
Chipkill
CPU cache
IBM POWER
POWER5
Dynamic random-access memory
Multi-core processor
RAM parity
IBM z10
Computer memory
Computer hardware
Computing

HC19Fault – Tolerant Design of the IBM POWER6 Microprocessor.v6.ppt

Add to Reading List

Source URL: www.hotchips.org

Download Document from Source Website

File Size: 1,35 MB

Share Document on Facebook

Similar Documents

Digital media / Chipkill / Dynamic random-access memory / RAM parity / Soft error / DIMM / CPU cache / Error detection and correction / DDR3 SDRAM / Computer memory / Computer hardware / Computing

LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems ∗ Aniruddha N. Udipi† † Naveen Muralimanohar‡

DocID: 11V2b - View Document

Data / Soft error / Dynamic random-access memory / Memory scrubbing / Chipkill / Hamming code / Error detection and correction / RAM parity / Random-access memory / Computer memory / Computing / Information

An Empirical Study of Memory Hardware Errors in A Server Farm∗ Xin Li Michael C. Huang Kai Shen University of Rochester

DocID: 10Tf2 - View Document

DIMM / Dynamic random-access memory / ProLiant / Blade server / RAM parity / Server / Xeon / Random-access memory / Chipkill / Computer memory / Computer hardware / Computing

How memory RAS technologies can enhance the uptime of HP ProLiant servers: Reduce server crash rate by approximately 85% - Technical white paper

DocID: Zxrq - View Document

POWER6 / Chipkill / CPU cache / IBM POWER / POWER5 / Dynamic random-access memory / Multi-core processor / RAM parity / IBM z10 / Computer memory / Computer hardware / Computing

HC19Fault – Tolerant Design of the IBM POWER6 Microprocessor.v6.ppt

DocID: W83Y - View Document