Xilinx

Results: 517



#Item
31Digilent Spartan-3 System Board  www.digilentinc.com Revision: June 18, 2004

Digilent Spartan-3 System Board www.digilentinc.com Revision: June 18, 2004

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Source URL: jl.web.free.fr

Language: English - Date: 2006-03-03 16:26:07
32322  IEEE TRANSACTIONS ON EDUCATION, VOL. 56, NO. 3, AUGUST 2013 A Lab Project on the Design and Implementation of Programmable and Configurable Embedded Systems

322 IEEE TRANSACTIONS ON EDUCATION, VOL. 56, NO. 3, AUGUST 2013 A Lab Project on the Design and Implementation of Programmable and Configurable Embedded Systems

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Source URL: www.inesc-id.pt

Language: English - Date: 2013-09-24 07:24:06
33Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs HIRAK KASHYAP and RICARDO CHAVES, INESC-ID, IST, Universidade de Lisboa The dynamic partial reconfiguration functionality of FPGAs can be attacked,

Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs HIRAK KASHYAP and RICARDO CHAVES, INESC-ID, IST, Universidade de Lisboa The dynamic partial reconfiguration functionality of FPGAs can be attacked,

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Source URL: www.inesc-id.pt

Language: English - Date: 2016-02-23 14:14:05
34P ROGRAMME INS É DITION 2013 Projet MetaLibM D OCUMENT SCIENTIFIQUE

P ROGRAMME INS É DITION 2013 Projet MetaLibM D OCUMENT SCIENTIFIQUE

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Source URL: metalibm.org

Language: English - Date: 2016-03-11 11:06:59
35P4FPGA: High Level Synthesis for Networking Han Wang, Ki Suh Lee, Vishal Shrivastav, Hakim Weatherspoon Cornell University 1  Introduction

P4FPGA: High Level Synthesis for Networking Han Wang, Ki Suh Lee, Vishal Shrivastav, Hakim Weatherspoon Cornell University 1 Introduction

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Source URL: conferences.sigcomm.org

Language: English - Date: 2016-08-02 16:10:05
36RISC-V on Sakura-G Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria  Motivation

RISC-V on Sakura-G Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation

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Source URL: www.iaik.tugraz.at

Language: English - Date: 2015-09-08 06:00:03
371300 Henley Court Pullman, WA6306 www.digilentinc.com  Nexys Video™ FPGA Board Reference Manual

1300 Henley Court Pullman, WA6306 www.digilentinc.com Nexys Video™ FPGA Board Reference Manual

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Source URL: www.europractice.stfc.ac.uk

Language: English - Date: 2016-02-25 10:46:40
38ISSN No: International Journal & Magazine of Engineering, Technology, Management and Research A Peer Reviewed Open Access International Journal

ISSN No: International Journal & Magazine of Engineering, Technology, Management and Research A Peer Reviewed Open Access International Journal

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Source URL: www.ijmetmr.com

Language: English - Date: 2015-07-08 03:14:43
39Evaluation Boards for SuperSpeed USB-to-FIFO Bridge ICs HSMC & FMC connectivity options facilitating deployment into FPGA-based designs 9th SeptemberTo encourage the widespread utilisation of its highly costeffec

Evaluation Boards for SuperSpeed USB-to-FIFO Bridge ICs HSMC & FMC connectivity options facilitating deployment into FPGA-based designs 9th SeptemberTo encourage the widespread utilisation of its highly costeffec

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Source URL: www.ftdichip.com

Language: English - Date: 2015-09-09 02:42:19
40Automated IP Integration: Gaining Cycle Time Advantage by Dr. Stefan Scharfenberg Senior Staff Engineer Motorola, SoCTD

Automated IP Integration: Gaining Cycle Time Advantage by Dr. Stefan Scharfenberg Senior Staff Engineer Motorola, SoCTD

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Source URL: www.steinwrites.com

Language: English - Date: 2009-03-19 17:34:19