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Computer memory / Central processing unit / Branch predictor / Hazard / CPU cache / Dynamic random-access memory / Dynamic voltage scaling / Microarchitecture / Design closure / Computer hardware / Electronic engineering / Computer architecture


Identifying and Predicting Timing-Critical Instructions to Boost Timing Speculation Jing Xin and Russ Joseph Department of EECS Northwestern University
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Document Date: 2011-12-14 11:29:00

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File Size: 858,60 KB

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Porto Alegre / /

Company

Synopsys / Efficient Frontier / Intel / /

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USD / /

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Facility

Keywords Pipeline / Ld/St Port / Pipeline Timing / stall Razor / IF1 IF2 ID RF stall EX IF1 IF2 / /

IndustryTerm

purpose low-power processor / dynamic management / oracle processor / adaptive voltage tuning algorithms / boost energy-efficiency / low energy-delay / baseline processor / system software / energy-delay / energy savings / energy / tasks/applications / energy costs / execution hardware / energy-efficiency / power management / low-power embedded processor / sample chips / energy-delay results / energy efficiency / manufacturing / address generator hardware / dynamic adaption algorithms / non-negligible energy / /

MarketIndex

LSU / /

Organization

National Science Foundation / Northwestern University / Russ Joseph Department / Alpha ALU and Shifter/Branch Unit / Central Intelligence Agency / Computer Systems Organization / /

Person

Distance Counter / Jing Xin / Russ Joseph / /

Position

Forward Short Simulation Long Simulation Hill Climbing Sampling Fuzzy Controller / IF1 IF2 ID stall RF MEM1 MEM1 MEM2 WB / MEM1 MEM2 WB / Fuzzy Controller / WB / Reliability General / designer / IF1 IF2 ID flush ID flush IF2 flush IF1 MEM1 MEM2 WB / representative / / controller / /

ProgrammingLanguage

C / Verilog / /

RadioStation

Wall 0 / /

Technology

Alpha / tuning algorithms / diagnostic tests / low-power embedded processor / 0.95 0.85 0.75 0.65 20 40 60 Chip / purpose low-power processor / block cipher / 100 Chips / Cache Memory / SRAM / Their Descriptions Our processor / one chip / Verilog / dynamic adaption algorithms / 100 sample chips / training algorithm / oracle processor / three adaptive voltage tuning algorithms / simulation / baseline processor / 6 Experimental Setup Processor / /

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