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Retiming
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#	Item
11	Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-01 16:05:11 Digital electronics Electronic design Formal methods And-inverter graph Retiming Logic synthesis Automatic test pattern generation Field-programmable gate array Sequential logic Electronic engineering Electronics Electronic design automation
12	Microsoft Word - haig09.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-03-23 19:52:58 Electronic design automation Electronic design Logic in computer science And-inverter graph Retiming Logic optimization Combinational logic Automatic test pattern generation Logic programming Electronic engineering Formal methods Digital electronics
13	Microsoft Word - haig14.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-05-20 20:12:25 Digital electronics Electronic design And-inverter graph Retiming Logic optimization Automatic test pattern generation Combinational logic Formal verification Logic programming Electronic engineering Formal methods Electronic design automation
14	Fast Minimum-Register Retiming via Binary Maximum-Flow Alan Mishchenko Aaron Hurst Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-11-20 10:30:53 Formal methods Electronics Retiming Electronic design automation Maximum flow problem Flow network Digital electronics Ford–Fulkerson algorithm Logic gate Network flow Electronic engineering Mathematics
15	Microsoft Word - SeqVerification08.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-02-17 18:15:49 Logic in computer science Mathematics Formal methods Computer memory Automata theory Rewriting Retiming Combinational logic Flip-flop Theoretical computer science Digital electronics Electronic engineering
16	Microsoft Word - EndtoEndRetiming6.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-05-01 11:48:41 Electronic design automation Clock signal Retiming Operations research Electrical circuits Clock skew Physical design Clock distribution network Mathematical optimization Electronic engineering Formal methods Electronics
17	Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappe Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-09-11 21:52:58 Digital electronics Electrical circuits Diagrams And-inverter graph Field-programmable gate array Static timing analysis Propagation delay Logic synthesis Retiming Electronic engineering Electronic design automation Formal methods
18	Microsoft Word - minreg-fmcad-final3.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-07-30 11:41:26 Combinatorial optimization Formal methods Combinatorics Retiming Maximum flow problem Flow network Minimum cut Cut Minimum-cost flow problem Network flow Graph theory Mathematics
19	Scalably-Verifiable Sequential Synthesis Robert Brayton Alan Mishchenko Department of EECS, University of California, Berkeley Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-10-02 14:31:33 Electronic design automation Digital electronics Logic in computer science Electrical circuits And-inverter graph Retiming Automatic test pattern generation Formal verification Combinational logic Electronic engineering Formal methods Theoretical computer science
20	Merging Nodes Under Sequential Observability Michael L. Case1,2 1 Victor N. Kravets3 Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-04-02 23:52:50 Electronic design automation Logic in computer science Theoretical computer science Scan chain Logic optimization And-inverter graph Combinational logic Retiming Algorithm Electronic engineering Formal methods Digital electronics

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